Datasheet

Embedded Flash memory RM0352
36/138 DocID024647 Rev 1
6.3.6 Unlock registers
The unlock registers UNLOCKM and UNLOCKL form together the special 64-bit code that
must match the two unlock words in the Flash (for more information see Section 6.5: Flash
protection (ready state).
6.3.7 LFSR register
The LFSR register will be initialized with all ones when the MASS READ command is written
to the COMMAND register. Then every read value is put through the LFSR. The result of the
MASS read is available for readout via the APB bus.
6.4 AHB-Lite
If the processor wants to address the Flash wrapper (READ ONLY), then it has to use the
most significant halfword specified in Table 23. The least significant halfword of the AHB
address will determine if we are addressing the Flash.
Table 22. Flash 50 ns access time from specifications
(1)
FlashConfig[5:4] FlashConfig[0] = 0 (not registered) FlashConfig[0] = 1 (registered)
00 (0 wait states) 16 MHz (16 DMIPS) 20 MHz (14 DMIPS)
01 (1 wait states)
20 MHz (14 DMIPS) /
26 MHz (19 DMIPS)
40 MHz (22 DMIPS)
(2)
10 (2 wait states) 40 MHz (22 DMIPS)
(2)
40 MHz (16 DMIPS)
11 (3 wait states) Not functional 80 MHz 80 MHz (32 DMIPS)
1. DMIPS for Dhrystone MIPS
®
.
2. The use of registered data is equivalent to the use of a wait state in term, of Flash access. But for the same
performance, the use of registered data is advisable for power saving.
Table 23. Flash address mapping
Parameter Value
Address [31:16] 0x1000
Flash range [15:0] Refer to Table 2: Memory table on page 14.