Datasheet

Clock and reset management unit RM0352
30/138 DocID024647 Rev 1
Table 15. CRMU_ECCR0
(1)
Address Bit Field name Reset R/W Description
CRMU_BASE + 0x10
0 PRAM_SINGLE_ERR 1'b0 R
ECC single error
correction signal
1 PRAM_DOUBLE_ERR 1'b0 R
ECC double error
detection signal
7:2 PRAM_FAIL_BIT 6'b0 R
ECC fail bit position
provided after single error
correction
15:8 RESERVED 8'b0 - -
31:16 PRAM_FAIL_ADDR 16'b0 R ECC fail address
1. This register is cleared on read.
Table 16. CRMU_ECCR1
Address Bit Field name Reset R/W Description
CRMU_BASE + 0x14
0 ECC_BYPASS 1'b0 R/W Bypass the ECC
1 ECC_DEBUG 1'b0 R/W
Put the ECC in debug
mode used for test only