Datasheet

DocID024647 Rev 1 29/138
RM0352 Clock and reset management unit
137
2. The field HS_OSC_SEL is programmed to select the clock output from the 3-way
clock-switch. It is the root point for the processor clock. It can be programmed as per
Table 12.
1. The 80 MHz clock is passed through a programmable clock divider to generate the
UART clock. If the field UART_DIVFACTOR is written with 0x0 or 0x1 the clock will not
be divided otherwise the clock will be divided by a value in the range 2, 3 to 127.
Table 12. Processor clock root selection
HS_OSC_SEL [7:6] Processor clock
00 80 MHz clock
01 32 KHz clock
10 External single ended clock
11 External single ended clock
Table 13. CRMU_CCR1
Address Bit Field name Reset R/W Description
CRMU_BASE + 0x8 6:0 UART_DIVFACTOR 7'b0 R/W UART clock divide factor
Table 14. CRMU_CCR2
Address Bit Field name Reset R/W Description
CRMU_BASE + 0xC
0 GPIO_EN 1'b0 R/W Enable for GPIO
1 UART_EN 1'b0 R/W Enable for UART
2 SPI_EN 1'b0 R/W Enable for SPI
3 I2C1_EN 1'b0 R/W Enable for I
2
C1
4 I2C2_EN 1'b0 R/W Enable for I
2
C2
5 - 8 RESERVED RESERVED
9 WDG_EN 1'b0 R/W Enable for WDG
10 TIMER0_EN 1'b0 R/W Enable for TIMER0
11 TIMER1_EN 1'b0 R/W Enable for TIMER1
12 TIMER2_EN 1'b0 R/W Enable for TIMER2
13 TIMER3_EN 1'b0 R/W Enable for TIMER3
14 TIMER4_EN 1'b0 R/W Enable for TIMER4
15 TIMER5_EN 1'b0 R/W Enable for TIMER5
16 TIMER6_EN 1'b0 R/W Enable for TIMER6
17 TIMER7_EN 1'b0 R/W Enable for TIMER7