Datasheet

Clock and reset management unit RM0352
24/138 DocID024647 Rev 1
5.2.10 SysTick clock
The SysTick timer is clocked on the processor clock.
5.2.11 SPI clock
The SPI IP has two clock inputs: one for the APB interface and one for the serial
receive/transmit feature. Both are clocked with a clock synchronous to the processor clock.
The serial clock can be divided by a factor of 2 to 254 by a step of two through the
CPSDVSR field of the SSPCPSR register (see Table 101: SSPCPSR register bit
assignments on page 107).
5.2.12 APB peripherals
To provide low power implementation all APB peripherals in the Brain device may have their
clocks gated off by writing to a bit in the CRMU_CCR2 register (see Table 14: CRMU_CCR2
on page 29).
5.3 Reset generation
5.3.1 General description
The Brain device contains various sources of reset: a power-on reset signal generated by
the POR circuitry and a brown out reset BOR which occurs when the battery level has fallen
below a certain threshold. In addition there are five internal events which cause various
parts of the chip to be reset.
The processor reset is generated by a combination of the POR, BOR, the error code
correction (ECC) reset, the watchdog reset, the system reset request from the debugger,
the recall done signal output from the Flash controller circuit, and the lockup signal output
from the processor.
The Flash controller is reset by a combination of the POR, BOR, ECC reset, watchdog
reset, system reset request, and lockup event of the processor, the recall signal does not
reset the Flash controller.
The Cortex-M0 debugger is reset only by the POR and the BOR signals this means that
none of the internal reset events should affect the debug session.
The timers are reset by the POR and the BOR signals.