Datasheet
DocID024647 Rev 1 23/138
RM0352 Clock and reset management unit
137
5.2.2 RC 80 MHz clock
The 80 MHz clock is generated by an on-chip RC oscillator and is accurate to within
1 percent.
5.2.3 RC 32 kHz clock
The 32 kHz clock is generated by an on-chip RC oscillator and is accurate to within
1 percent.
5.2.4 External clock
The external clock is generated by a single ended clock source operating up to 80 MHz.
5.2.5 System clock
The system clock has 3 possible sources; the field HS_OSC_SEL in CRMU_CCR0 is used
to switch between the various sources.
• HS_OSC_SEL[0] selects between either RC_32K_CLK or RC_80M_CLK.
• HS_OSC_SEL[1] can be used to select the external clock as source for the system
clock.
• If HS_OSC_SEL[1] is set to 0 which is the default either RC_32K_CLK or
RC_80M_CLK will be selected as system clock.
In order to switch to the external clock the bit EXT_XO_EN in the CRMU_CCR0 register
(see Table 9: CRMU_CCR0 on page 28) must be set to 1 to enable the external clock.
5.2.6 I
2
C clocks
Each I
2
C IP has two clock inputs - one for the APB interface which is synchronous to the
processor clock and one for the baud rate generation the source of which is the system
clock divided by 3.
5.2.7 UART clocks
The UART has two clock inputs - one for the APB interface which is synchronous to the
processor clock and one for the baud rate generation the source of which is the system
clock divided by the programmable division factor written to the UART_DIVFACTOR field of
the CRMU_CCR1 register (see Table 13: CRMU_CCR1 on page 29).
5.2.8 Dual timers clocks
The timers 3 to 0 are clocked with a clock synchronous to the processor clock. The
timers 7 to 4 are clocked with the 32 KHz resynchronized on the system clock. When the
system clock is equal or lower than 32 KHz, timers 7 to 4 are not functional. LS_OSC_SEL
bit in the CRMU_CCR0 register (see Table 9: CRMU_CCR0 on page 28) allows choosing
32 KHz source between an internal oscillator and external single ended clock.
5.2.9 Watchdog clock
The watchdog is clocked on 32 KHz. The LS_OSC_SEL bit in the CRMU_CCR0 register
allows choosing 32 KHz source between an internal oscillator and external single ended
clock.