Datasheet

DocID024647 Rev 1 21/138
RM0352 Clock and reset management unit
137
5 Clock and reset management unit
5.1 Introduction
The Brain CRMU implements the clock and reset generation for the Brain device. The Brain
CRMU is accessible through an APB interface.
5.2 Clock generation
5.2.1 General description
The system clock can be selected from one of three clocks:
• 80 MHz RC oscillator clock
• 32 kHz RC oscillator clock
Note: Real frequency is 32.768 kHz. However, it is called 32 kHz throughout the document to
simplify.
• External single ended input clock
There are four clock dividers in the CRMU which divide the system clock before it is used to
generate the clocks for the peripherals, processor, and memories.
The source of the clock for the processor can be selected from four possible sources:
• System clock divided by 5 (default)
• System clock divided by 2, 4, 6, 8, 10, 16, 20, 32
• System clock divided by 3
• System clock
By default the system clock divided by 5 is selected as the root point for the AHB and APB
clocks, this is to meet the access time requirements of the Flash memory which is 50 ns. In
the Brain device the processor boots from the information block of the Flash so it is not
possible to boot with the 80 MHz RC oscillator clock. The user can switch to the high speed
clock after the program has been copied into the program RAM.
The system contains a low speed clock which is used for the timers and the watchdog
circuitry. The low speed clock has 2 possible sources:
• 32 KHz RC oscillator clock
• External single ended input clock