Datasheet

GPIO RM0352
20/138 DocID024647 Rev 1
Table 5. GPIO configuration registers
Address Bit Field name Reset R/W Description
0x00 14 GPIO_WDATA 14'h0000 R/W IO0 to IO10 output value
0x04 14 GPIO_DIR 14'h0000 R/W
Data direction register (1 bit per GPIO):
– 0: input
– 1: output
0x08 14 GPIO_PE 14'h3FFF R/W
Pull enable (1 bit per GPIO)
– 0: pull disabled
– 1: pull enabled
0x0C 32 GPIO_MODE_W 32'h0000_0000 R/W
2 bits mux selection for each I/Os: [1:0] conf. IO0;
[3:2] conf. IO1, etc.
0x10 14 GPIO_IS 14'h0000 R/W
Interrupt sense register (1 bit per GPIO):
– 0: edge detection
– 1: level detection
0x14 14 GPIO_IBE 14'h0000 R/W
Interrupt both-edges register (1 bit per GPIO):
– 0: single edge
– 1: both edges
0x18 14 GPIO_IVE 14'h0000 R/W
Interrupt event register (1 bit per GPIO):
– 0: falling edge / low level
– 1: rising edge / high level
0x1C 14 GPIO_IE 14'h0000 R/W
Interrupt mask register (1 bit per GPIO):
–0: masked
– 1: not masked
0x20 14 GPIO_RIS 14'h0000 RMW Raw interrupt status register (1 bit per GPIO)
0x24 14 GPIO_MIS 14'h0000 RMW Masked interrupt status register(1 bit per GPIO)
0x28 14 GPIO_IC 14'h0000 W
Interrupt clear register (1 bit per GPIO):
– 0: no effect
– 1: clear interrupt
0x2C 2 I2C_CONF 2'h3 R/W
Bit 0 set to 1 enable the I
2
C mode on the pads master
(IO7 and IO8)
Bit 1 set to 1 enables the I
2
C mode on the pads slave
(IO3)
Table 6. Edge/level and rising/falling edge interrupt configuration
(1)
Configuration
Interrupt mode
Falling edge Rising edge Both edges Low level High level
GPIOIS 0 0 0 1 1
GPIOIBE 0 0 1 NA NA
GPIOIEV 0 1 NA 0 1
1. Each I/O has to be configured according to the 3 bits above to detect a different shape of interrupt event.