Datasheet

DocID024647 Rev 1 19/138
RM0352 GPIO
137
4 GPIO
The Brain device proposes 11 programmable I/Os.
Each GPIO provides one programmable input or output that can be controlled in three
modes:
• GPIO Port mode: direction and data are programmed through registers (see Table 5:
GPIO configuration registers)
• Serial 0 and Serial 1 modes: the GPIO becomes a peripheral input or output line (see
Table 4: GPIO alternate options)
Each GPIO can generate an interrupt independently to the selected mode. Interrupts are
generated depending on a level or edge. (See Table 5: GPIO configuration registers and
Table 6: Edge/level and rising/falling edge interrupt configuration for more details).
The base address of the GPIO block in the Brain memory map is 0xA000_0000.
Table 4. GPIO alternate options
(1) (2) (3)
1. The white color covers resources dedicated to the fix 1.8 V power supply while the gray one are pin
resources on the wide range from 1.8 V to 3.3 V power supply.
2. In serial mode 0, I/O 3 MUST be configured as an I
2
C mode pad (i.e. I2C_CONF[1] = 1).
In serial mode 1 and GPIO port mode, IO3 MUST be configured as normal mode (I2C_CONF[1] = 0).
3. After reset, IO6 outputs the 80 MHz clock divided by five.
Pin
no.
Ref. Pull
Serial mode 0 Serial mode 1 GPIO port mode
GPIO_MODE_W = “00” GPIO_MODE_W = “01” GPIO_MODE_W = “10”
Type Signal Type Signal Type Signal
2 IO0 Down I/O
SW_TDIO/
JTAG TMS
I UART_CTS I/O GPIO0
3 IO1 Down I
SW_TCK/J
TAG TCK
O UART_RTS I/O GPIO1
4IO2 Up I I
2
C2_SCL O UART_TXD I/O GPIO2
6 IO3 Down I/O I
2
C2_SDA I UART_RXD I/O GPIO3
7 IO4 Down O JTAG TDO I NA I/O GPIO4
8 IO5 Down I JTAG TDI I NA I/O GPIO5
9 IO8 Up I/O I
2
C1 SDA O SPI_OUT I/O GPIO8
10 IO6 Down O
Divided
CLK80M
O CLK32K I/O GPIO6
11 IO7 Up I/O I
2
C1 SCL I/O SPI_CLK I/O GPIO7
15 IO10 Down I NA I SPI_IN I/O GPIO10
16 IO9 Up I NA I SPI_CS I/O GPIO9