Datasheet

DocID024647 Rev 1 17/138
RM0352 Interrupts
137
3 Interrupts
Interrupts are handled by the Cortex-M0 “Nested Vector Interrupt controller” (NVIC). The
NVIC controls specific Cortex-M0 interrupts (address 0x0 to 0x3C) as well as 32 user
interrupts (address 0x40 to 0xBC). In the Brain device , user interrupts have been
connected to the interrupt signals of the different peripherals (GPIO, Flash controller, timers
UART, SPI, I
2
C, RAM bank0, WDG). Those interrupts can be controlled via the ISER, ICER,
ISPR and ICPR registers (see the “DUI0497A_cortex_m0_r0p0_generic_ug” document).
Table 3. Interrupt vectors
(1)
Position Priority
Type of
priority
Acronym Description Address
Initial main SP 0x0000_0000
-3 Fixed Reset Reset 0x0000_0004
-2 Fixed NMI Non-maskable interrupt. 0x0000_0008
-1 Fixed HardFault All class of fault 0x0000_000C
- RESERVED RESERVED RESERVED 0x0000_0010 - 0x0000_0028
3 Settable SVCall
System service call via SWI
instruction
0x0000_002C
- RESERVED RESERVED RESERVED 0x0000_0030 - 0x0000_0034
5 Settable PenSV
Pendable request for system
service
0x0000_0038
6 Settable SysTick System tick timer 0x0000_003C
0 Init 0 Settable GPIO GPIO bus interrupt 0x0000_0040
1 Init 0 Settable NVM Non-volatile memory controller 0x0000_0044
2 Init 0 RESERVED RESERVED RESERVED 0x0000_0048
3 Init 0 RESERVED RESERVED RESERVED 0x0000_004C
4 Init 0 RESERVED RESERVED RESERVED 0x0000_0050
5 Init 0 RESERVED RESERVED RESERVED 0x0000_0054
6 Init 0 Settable UART1 UART1 interrupt 0x0000_0058
7 Init 0 Settable SPI1 SPI1 interrupt 0x0000_005C
8 Init 0 Settable I2C1 I
2
C 1 interrupt 0x0000_0060
9 Init 0 Settable I2C2 I
2
C 2 interrupt 0x0000_0064
10 Init 0 Settable ECC
RAM bank0 controller ECC
interrupt
0x0000_0068
11 Init 0 Settable WDG Watchdog interrupt 0x0000_006C
12 Init 0 Settable TIMER0A Dual Timer0A 0x0000_0070
13 Init 0 Settable TIMER0B Dual Timer0B 0x0000_0074
14 Init 0 Settable TIMER1A Dual Timer1A 0x0000_0078
15 Init 0 Settable TIMER1B Dual Timer1B 0x0000_007C