Datasheet

DocID024647 Rev 1 15/138
RM0352 System and memory overview
137
2.3 Embedded SRAM
The Brain device features up to 128 KBytes of static SRAM (RAM bank0 + RAM bank1). It
can be accessed as bytes, half words (16 bits) or full words (32 bits). This memory can be
addressed at maximum system clock frequency without wait state.
Error code correction check
The user can disable the ECC check for 64 Kbytes capacity RAM bank0 using the option bit
ECC_BYPASS in the user option ECC CRMU_ECCR1 register.
The data bus width is 39 bits because 7 bits are available for an error code correction check
in order to increase memory robustness.
The ECC bits are computed and stored when writing into the RAM bank0. Then, they are
automatically checked when reading. If one bit fails the data read is corrected and an
interrupt is generated. If two or more bits fail the corrupted data is replaced by the data
0xDEAD_DEAD and a reset is generated. The SRAM ECC error flags
(PRAM_SINGLE_ERR and PRAM_DOUBLE_ERR) are available in the CRMU_ECCR0
status register.
2.4 Flash memory overview
The Flash memory is composed of two distinct physical areas:
• The main Flash memory block. It contains the application program and user data if
necessary.
• The information block. System memory which contains the proprietary boot loader
code.
Please refer to Section 6: Embedded Flash memory on page 31 for more details.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements the logic necessary to carry out the Flash memory operations
(Program/Erase) controlled through the Flash registers.
0xE010_0000 - 0xEFFF_FFFF
Device
255 MBytes RESERVED (error response)
0xF000_0000 - 0xFFFF_FFFF 256 MBytes RESERVED (error response)
Table 2. Memory table (continued)
Address
Cortex-M0
address map
Size Remap = 0 Remap = 1