Datasheet

UART (universal asynchronous receive transmit) RM0352
132/138 DocID024647 Rev 1
12.6.12 Masked interrupt status register, UARTMIS
The UARTMIS register is the masked interrupt status register. It is a read-only register. This
register returns the current masked status value of the corresponding interrupt. A write has
no effect.
All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when
reset. The modem status interrupt bits are undefined after reset. Table 129 lists the register
bit assignments.
Table 129. UARTMIS register
Bits Name Function
15:11 - RESERVED, read as zero, do not modify.
10 OEMIS Overrun error masked interrupt status. Returns the masked interrupt state of the
UARTOEINTR interrupt.
9 BEMIS Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR
interrupt.
8 PEMIS Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR
interrupt.
7 FEMIS Framing error masked interrupt status. Returns the masked interrupt state of the
UARTFEINTR interrupt.
6 RTMIS Receive timeout masked interrupt status. Returns the masked interrupt state of the
UARTRTINTR interrupt.
5 TXMIS Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR
interrupt.
4 RXMIS Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR
interrupt.
3 DSRMMIS nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the
UARTDSRINTR interrupt.
2 DCDMMIS nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the
UARTDCDINTR interrupt.
1CTSMMISnUARTCTS modem masked interrupt status. Returns the masked interrupt state of the
UARTCTSINTR interrupt.
0RIMMISnUARTRI modem masked interrupt status. Returns the masked interrupt state of the
UARTRIINTR interrupt.