Datasheet

DocID024647 Rev 1 131/138
RM0352 UART (universal asynchronous receive transmit)
137
12.6.11 Raw interrupt status register, UARTRIS
The UARTRIS register is the raw interrupt status register. It is a read-only register. This
register returns the current raw status value, prior to masking, of the corresponding
interrupt. A write has no effect.
Caution: All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when
reset. The modem status interrupt bits are undefined after reset.
Table 128 lists the register bit assignments.
Table 128. UARTRIS register
Bits Name Function
15:11 - RESERVED, read as zero, do not modify.
10 OERIS Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
9 BERIS Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
8 PERIS Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
7 FERIS Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
6 RTRIS Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR
interrupt.
(1)
5 TXRIS Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
4 RXRIS Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
3 DSRRMIS nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR
interrupt.
2 DCDRMIS nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR
interrupt.
1CTSRMISnUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR
interrupt.
0RIRMISnUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR
interrupt.
1. In this case the raw interrupt cannot be set unless the mask is set, this is because the mask acts as an enable for power
saving. That is, the same status can be read from UARTMIS and UARTRIS for the receive timeout interrupt.