Datasheet

DocID024647 Rev 1 129/138
RM0352 UART (universal asynchronous receive transmit)
137
Program the control registers as follows:
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by setting the FEN bit to 0 in the line control register,
UARTLCR_H in Section 12.6.7 on page 126.
4. Reprogram the UARTCR register.
5. Enable the UART.
12.6.9 Interrupt FIFO level select register, UARTIFLS
The UARTIFLS register is the interrupt FIFO level select register. You can use this register
to define the FIFO level that triggers the assertion of UARTTXINTR and UARTRXINTR.
The interrupts are generated based on a transition through a level rather than being based
on the level. That is, the interrupts are generated when the fill level progresses through the
trigger level.
The bits are reset so that the trigger level is when the FIFOs are at the half-way mark.
Table 126 lists the register bit assignments.
Table 126. UARTIFLS register
Bits Name Function
15:6 - RESERVED, do not modify, read as zero.
5:3 RXIFLSEL Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows:
b000 = receive FIFO becomes ≥ 1/8 full
b001 = receive FIFO becomes ≥ 1/4 full
b010 = receive FIFO becomes ≥ 1/2 full
b011 = receive FIFO becomes ≥ 3/4 full
b100 = receive FIFO becomes ≥ 7/8 full
b101 - b111 = RESERVED.
2:0 TXIFLSEL Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows:
b000 = transmit FIFO becomes ≤ 1/8 full
b001 = transmit FIFO becomes ≤ 1/4 full
b010 = transmit FIFO becomes ≤ 1/2 full
b011 = transmit FIFO becomes ≤ 3/4 full
b100 = transmit FIFO becomes ≤ 7/8 full
b101 - b111 = RESERVED.