Datasheet

DocID024647 Rev 1 125/138
RM0352 UART (universal asynchronous receive transmit)
137
The maximum error using a 6-bit UARTFBRD register = 1/64 × 100 = 1.56%. This occurs
when m = 1, and the error is cumulative over 64 clock ticks.
Table 121 lists some typical bit rates and their corresponding divisors when UARTCLK is
7.3728MHz. These values do not use the fractional divider so the value in the UARTFBRD
register is zero.
Table 122 lists some required bit rates and their corresponding integer and fractional divisor
values and generated bit rates when UARTCLK is 4 MHz.
Table 121. Typical baud rates and integer divisors when UARTCLK = 7.3728 MHz
Programmed integer divisor Bit rate (bps)
0x1 460800
0x2 230400
0x4 115200
0x6 76800
0x8 57600
0xC 38400
0x18 19200
0x20 14400
0x30 9600
0xC0 2400
0x180 1200
0x105D 110
Table 122. Integer and fractional divisors for typical baud rates when
UARTCLK = 4 MHz
Programmed
integer divisor
Programmed
fractional divisor
Required bit rate
(bps)
Generated bit
rate (bps)
Error%
0x1 0x5 230400 231911 0.656
0x2 0xB 115200 115101 0.086
0x3 0x10 76800 76923 0.160
0x6 0x21 38400 38369 0.081
0x11 0x17 14400 14401 0.007
0x68 0xB 2400 2400 ~0
0x8E0 0x2F 110 110 ~0