Datasheet

UART (universal asynchronous receive transmit) RM0352

120/138 DocID024647 Rev 1

12.6 Register descriptions

This section describes the UART registers. Table 114 lists the cross references to individual

registers.

12.6.1 Data register, UARTDR

The UARTDR register is the data register. For words to be transmitted:

• If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO.

• If the FIFOs are not enabled, data is stored in the transmitter holding register (the

bottom word of the transmit FIFO).

The write operation initiates transmission from the UART. The data is prefixed with a start

bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The

resultant word is then transmitted.

For received words:

• If the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and

overrun) is pushed onto the 12-bit wide receive FIFO.

• If the FIFOs are not enabled, the data byte and status are stored in the receiving

holding register (the bottom word of the receive FIFO).

The received data byte is read by performing reads from the UARTDR register along with

the corresponding status information. The status information can also be read by a read of

the UARTRSR/UARTECR register as shown in Table 116.

0xFEC UARTPeriphID3 RO 0x00 8

UARTPeriphID3 register - see Section :

UARTPeriphID3 register on page 135

0xFF0 UARTPCellID0 RO 0x0D 8

UARTPCellID0 register - see Section : UARTPCellID0

0xFF4 UARTPCellID1 RO 0xF0 8

UARTPCellID1 register - see Section : UARTPCellID1

0xFF8 UARTPCellID2 RO 0x05 8

UARTPCellID2 register - see Section : UARTPCellID2

0xFFC UARTPCellID3 RO 0xB1 8

UARTPCellID3 register - see Section : UARTPCellID3

1. The value depends on the revision of the UART. See Table 133 on page 134.

Table 114. UART register summary (continued)

Offset Name Type Reset Width Description