Datasheet
System and memory overview RM0352
12/138 DocID024647 Rev 1
2 System and memory overview
2.1 System architecture
The main system consists of:
• One master:
– Cortex-M0 core AHB bus
• Four slaves:
– Internal 64 KByte SRAM for program or data with ECC referred as RAM bank0
– Internal 64 KByte SRAM for program or data referred as RAM bank1
– Internal 64 KByte Flash memory
– AHB to APB, which connects all the APB peripherals
These are interconnected using an AHB-Lite bus architecture as shown in Figure 1:
Figure 1. System architecture
Bus address decode
The bus address decode manages the access to slave peripherals through an AHB-Lite
protocol.
AHB2APB bridge (APB)
The AHB2APB bridge provides full synchronous connection between the AHB and the APB
bus. Refer to Table 2 for the address mapping of the peripherals connected to this bridge.
After each device reset, all APB peripheral clocks are disabled, except CRMU clock.
Before using a peripheral you have to enable its clock in the CCR2 register in the CRMU.
Note: The APB protocol does not support partial word access. 8- or 16-bit AHB access is
transformed into 32-bit access.
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