Datasheet

DocID024647 Rev 1 119/138
RM0352 UART (universal asynchronous receive transmit)
137
Table 114. UART register summary
Offset Name Type Reset Width Description
0x000 UARTDR RW 0x-- 12/8
Data register, UARTDR - see Section 12.6.1 on page
120
0x004
UARTRSR /
UARTECR
RW 0x00 4/0
Receive status register/error clear register,
UARTRSR/UARTECR - see Section 12.6.2 on page
121
0x008-0x014 RW 0x00 6 RESERVED
0x018 UARTFR RO
9'b-
10010--
-
9
Flag register, UARTFR - see Section 12.6.3 on page
122
0x01C RW 0x00 6 RESERVED
0x020 UARTILPR RW 0x00 8
IrDA low-power counter register, UARTILPR - see
Section 12.6.4 on page 123
0x024 UARTIBRD RW 0x0000 16
Integer baud rate register, UARTIBRD - see
Section 12.6.5 on page 124
0x028 UARTFBRD RW 0x00 6
Fractional baud rate register, UARTFBRD - see
Section 12.6.6 on page 124
0x02C UARTLCR_H RW 0x00 8
Line control register, UARTLCR_H - see Section 12.6.7
on page 126
0x030 UARTCR RW 0x0300 16
Control register, UARTCR - see Section 12.6.8 on page
127
0x034 UARTIFLS RW 0x12 6
Interrupt FIFO level select register, UARTIFLS - see
Section 12.6.9 on page 129
0x038 UARTIMSC RW 0x000 11
Interrupt mask set/clear register, UARTIMSC - see
Section 12.6.10 on page 130
0x03C UARTRIS RO 0x00- 11
Raw interrupt status register, UARTRIS - see
Section 12.6.11 on page 131
0x040 UARTMIS RO 0x00- 11
Masked interrupt status register, UARTMIS - see
Section 12.6.12 on page 132
0x044 UARTICR WO - 11
Interrupt clear register, UARTICR - see Section 12.6.13
on page 133
0x048 - - - - RESERVED
0x04C-0x07C - - - - RESERVED
0x080-0x08C - - - - RESERVED for test purposes
0x090-0xFCC - - - - RESERVED
0xFD0-0xFDC - - - - RESERVED for future ID expansion
0xFE0 UARTPeriphID0 RO 0x11 8
UARTPeriphID0 register - see Section :
UARTPeriphID0 register on page 134
0xFE4 UARTPeriphID1 RO 0x10 8
UARTPeriphID1 register - see Section :
UARTPeriphID1 register on page 134
0xFE8 UARTPeriphID2 RO 0x34
(1)
8
UARTPeriphID2 register - see Section :
UARTPeriphID2 register on page 134