Datasheet

UART (universal asynchronous receive transmit) RM0352
116/138 DocID024647 Rev 1
12.2 IrDA SIR block
The IrDA “Serial InfraRed” (SIR) block contains an IrDA SIR protocol ENDEC. The SIR
protocol ENDEC can be enabled for serial communication through signals nSIROUT and
SIRIN to an infrared transducer instead of using the UART signals UARTTXD and
UARTRXD.
If the SIR protocol ENDEC is enabled, the UARTTXD line is held in the passive state (HIGH)
and transitions of the modem status, or the UARTRXD line have no effect. The SIR protocol
ENDEC can receive and transmit, but it is half-duplex only, so it cannot receive while
transmitting, or transmit while receiving.
The IrDA SIR physical layer specifies a minimum 10 ms delay between transmission and
reception.
12.3 Baud rate generator
The baud rate generator contains free running counters that generate the internal ×16
clocks, Baud16 and IrLPBaud16 signals. Baud16 provides timing information for UART
transmit and receive control. Baud16 is a stream of pulses with a width of one UARTCLK
clock period and a frequency of 16 times the baud rate. IrLPBaud16 provides timing
information to generate the pulse width of the IrDA encoded transmit bit stream when in low-
power IrDA mode.
12.4 Interrupts
There are eleven maskable interrupts generated in the UART. These are combined to
produce five individual interrupt outputs and one that is the OR of the individual outputs:
• UARTRXINTR
• UARTTXINTR
• UARTRTINTR
• UARTMSINTR, that can be caused by:
– UARTRIINTR, because of a change in the nUARTRI modem status
– UARTCTSINTR, because of a change in the nUARTCTS modem status
– UARTDCDINTR, because of a change in the nUARTDCD modem status
– UARTDSRINTR, because of a change in the nUARTDSR modem status.
• UARTEINTR, that can be caused by:
– UARTOEINTR, because of an overrun error
– UARTBEINTR, because of a break in the reception
– UARTPEINTR, because of a parity error in the received character
– UARTFEINTR, because of a framing error in the received character.
• UARTINTR, this is an OR function of the five individual masked outputs.
Changing the mask bits in the interrupt mask set/clear register, UARTIMSC - see
Section 12.6.10 on page 130 enables or disables the individual interrupts. Setting the
appropriate mask bit HIGH enables the interrupt.
Provision of individual outputs and the combined interrupt output, allows using either
a global interrupt service routine, or modular device drivers to handle interrupts.