Datasheet

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RM0352 UART (universal asynchronous receive transmit)
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12 UART (universal asynchronous receive transmit)
The Brain device has one asynchronous serial ports (UART). The UART block is an IP
provided by ARM (PL011). Additional details about its functional blocks can be found in
“PrimeCell®UART(PL011) Technical Reference Manual”.
12.1 Features
The UART performs:
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device.
The CPU reads and writes data and control/status information through the AMBA APB
interface. The transmit and receive paths are buffered with internal FIFO memories enabling
up to 32-bytes to be stored independently in both transmit and receive modes.
The UART:
• Includes a programmable baud rate generator that generates a common transmit and
receive internal clock from the UART internal reference clock input, UARTCLK
• Offers similar functionality to the industry-standard 16C650 UART device
• Supports the following maximum baud rates:
– 921600 bps, in UART mode
– 460800 bps, in IrDA
®
mode
– 115200 bps, in low-power IrDA mode.
The UART operation and baud rate values are controlled by the line control register,
UARTLCR_H - see Section 12.6.7 on page 126 and the baud rate divisor registers (integer
baud rate register, UARTIBRD - see Section 12.6.5 on page 124 and fractional baud rate
register, UARTFBRD - see Section 12.6.6 on page 124).
The UART can generate:
• Individually maskable interrupts from the receive (including timeout), transmit,
• Modem status and error conditions
• A single combined interrupt so that the output is asserted if any of the individual
interrupts are asserted, and unmasked.
If a framing, parity, or break error occurs during reception, the appropriate error bit is set,
and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set
immediately and FIFO data are prevented from being overwritten.
It is possible to program the FIFOs to be 1-byte deep providing a conventional double
buffered UART interface.
The modem status input signals “Clear To Send” (CTS), “Data Carrier Detect” (DCD), “Data
Set Ready” (DSR), and “Ring Indicator” (RI) are supported. The output modem control lines,
“Request To Send” (RTS), and “Data Terminal Ready” (DTR) are also supported.
There is a programmable hardware flow control feature that uses the nUARTCTS input and
the nUARTRTS output to automatically control the serial data flow.