Datasheet

DocID024647 Rev 1 113/138
RM0352 SPI (serial peripheral interface)
137
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 112 shows the bit assignments.
SSPPCellID3 register
The SSPPCellID3 register characteristics are:
Purpose The SSPPCellID3 register is hard-coded and the fields within the
register determine the reset value.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table Table 96 on page 101.
Table 113 shows the bit assignments.
11.5 Interrupts
There are five interrupts generated by the PrimeCell SSP. Four of these are individual,
maskable, active-HIGH interrupts as follows:
SSPRXINTR PrimeCell SSP receive FIFO service interrupt request. See Section 11.5.1:
SSPRXINTR.
SSPTXINTR PrimeCell SSP transmit FIFO service interrupt request. See Section 11.5.2:
SSPTXINTR.
SSPRORINTR PrimeCell SSP receive overrun interrupt request. See Section 11.5.3:
SSPRORINTR
SSPRTINTR PrimeCell SSP time out interrupt request. See Section 11.5.4:
SSPRTINTR.
The fifth is a combined single interrupt SSPINTR.
You can mask each of the four individual maskable interrupts by setting the appropriate bits
in the SSPIMSC register. Setting the appropriate mask bit HIGH enables the interrupt.
Table 112. SSPPCellID2 register bit assignments
Bits Name Description
[15:8] RESERVED RESERVED, read undefined, must read as zeros
[7:0] SSPPCellID2 These bits read back as 0x05
Table 113. SSPPCellID3 register bit assignments
Bits Name Description
[15:8] RESERVED RESERVED, read undefined, must read as zeros
[7:0] SSPPCellID3 These bits read back as 0xB1