Datasheet

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RM0352 SPI (serial peripheral interface)
137
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 108 shows the bit assignments.
SSPPeriphID3 register
The SSPPeriphID3 register characteristics are:
Purpose The SSPPeriphID3 register is hard-coded and the fields within the
register determine the reset value.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 109 shows the bit assignments.
11.4.11 PrimeCell identification registers, SSPPCellID0-3
The SSPPCellID0-3 registers characteristics are:
Purpose The SSPPCellID0-3 registers are four 8-bit wide registers, that span
address locations 0xFF0-0xFFC. The registers can conceptually be
treated as a 32-bit register. The register is used as a standard cross-
peripheral identification system. The SSPPCellID register is set to
0xB105F00D.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 108. SSPPeriphID2 register bit assignments
Bits Name Description
[15:8] RESERVED RESERVED, read undefined, must read as zeros
[7:4] Revision These bits return the peripheral revision
[3:0] Designer1 These bits read back as 0x4
Table 109. SSPPeriphID3 register bit assignments
Bits Name Description
[15:8] RESERVED RESERVED, read undefined, must read as zeros
[7:0] Configuration These bits read back as 0x00