Datasheet

SPI (serial peripheral interface) RM0352
108/138 DocID024647 Rev 1
11.4.7 Raw interrupt status register, SSPRIS
The SSPRIS register characteristics are:
Purpose The SSPRIS register is the raw interrupt status register. It is an RO
register.
On a read this register gives the current raw status value of the
corresponding interrupt prior to masking. A write has no effect.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 103 shows the bit assignments.
11.4.8 Masked interrupt status register, SSPMIS
The SSPMIS register characteristics are:
Purpose The SSPMIS register is the masked interrupt status register. It is an
RO register. On a read this register gives the current masked status
value of the corresponding interrupt. A write has no effect.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 104 shows the bit assignments.
Table 103. SSPRIS register bit assignments
Bits Name Function
[15:4] RESERVED RESERVED, read as zero, do not modify
[3] TXRIS Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
[2] RXRIS Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
[1] RTRIS Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
[0] RORRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
Table 104. SSPMIS register bit assignments
Bits Name Function
[15:4] RESERVED RESERVED, read as zero, do not modify
[3] TXMIS Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
[2] RXMIS Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
[1] RTMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
[0] RORMIS Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR
interrupt