Datasheet

DocID024647 Rev 1 107/138
RM0352 SPI (serial peripheral interface)
137
Table 101 shows the bit assignments.
11.4.6 Interrupt mask set or clear register, SSPIMSC
The SSPIMSC register characteristics are:
Purpose The SSPIMSC register is the interrupt mask set or clear register. It is
an RW register.
On a read this register gives the current value of the mask on the
relevant interrupt. A write of 1 to the particular bit sets the mask,
enabling the interrupt to be read. A write of 0 clears the
corresponding mask.
All the bits are cleared to 0 when reset.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 102 shows the bit assignments.
Table 101. SSPCPSR register bit assignments
Bits Name Function
[15:8] - RESERVED, read unpredictable, must be written as 0.
[7:0] CPSDVSR Clock prescale divisor. Must be an even number from 2 - 254, depending on the
frequency of SSPCLK. The least significant bit always returns zero on reads.
Table 102. SSPIMSC register bit assignments
Bits Name Function
[15:4] RESERVED RESERVED, read as zero, do not modify.
[3] TXIM Transmit FIFO interrupt mask:
0: transmit FIFO half empty or less condition interrupt is masked.
1: transmit FIFO half empty or less condition interrupt is not masked.
[2] RXIM Receive FIFO interrupt mask:
0: receive FIFO half full or less condition interrupt is masked.
1: receive FIFO half full or less condition interrupt is not masked.
[1] RTIM Receive timeout interrupt mask:
0: receive FIFO not empty and no read prior to timeout period interrupt is masked.
1: receive FIFO not empty and no read prior to timeout period interrupt is not masked.
[0] RORIM Receive overrun interrupt mask:
0: receive FIFO written to while full condition interrupt is masked.
1: receive FIFO written to while full condition interrupt is not masked.