Datasheet

SPI (serial peripheral interface) RM0352
106/138 DocID024647 Rev 1
Table 100 shows the bit assignments.
11.4.5 Clock prescale register, SSPCPSR
The SSPCPSR register characteristics are:
Purpose The SSPCPSR is the clock prescale register and specifies the
division factor by which the input SSPCLK must be internally divided
before further use.
The value programmed into this register must be an even number
between 2 - 254. The least significant bit of the programmed number
is hard-coded to zero. If an odd number is written to this register,
data read back from this register has the least significant bit as zero.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 100. SSPSR register bit assignments
Bits Name Function
[15:5] - RESERVED, read unpredictable, should be written as 0.
[4] BSY PrimeCell SSP busy flag, RO:
0: SSP is idle.
1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.
[3] RFF Receive FIFO full, RO:
0: receive FIFO is not full.
1: receive FIFO is full.
[2] RNE Receive FIFO not empty, RO:
0: receive FIFO is empty.
1: receive FIFO is not empty.
[1] TNF Transmit FIFO not full, RO:
0: transmit FIFO is full.
1: transmit FIFO is not full.
[0] TFE Transmit FIFO empty, RO:
0: transmit FIFO is not empty.
1: transmit FIFO is empty.