Datasheet

DocID024647 Rev 1 105/138
RM0352 SPI (serial peripheral interface)
137
When the SSPDR is written to, the entry in the transmit FIFO, pointed
to by the write pointer, is written to. Data values are removed from the
transmit FIFO one value at a time by the transmit logic. It is loaded into
the transmit serial shifter, then serially shifted out onto the SSPTXD
pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-
justify data written to the transmit FIFO. The transmit logic ignores the
unused bits. Received data less than 16 bits is automatically right-
justified in the receive buffer.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 99 shows the bit assignments.
11.4.4 Status register, SSPSR
The SSPSR register characteristics are:
Purpose The SSPSR is an RO status register that contains bits that indicate
the FIFO fill status and the PrimeCell SSP busy status.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96 on page 101.
Table 99. SSPDR register bit assignments
Bits Name Function
[15:0] DATA Transmit/receive FIFO:
Read: receive FIFO.
Write: transmit FIFO.
You must right-justify data when the PrimeCell SSP is programmed for a data size that is less
than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic
automatically right-justifies.