Datasheet

SPI (serial peripheral interface) RM0352
104/138 DocID024647 Rev 1
11.4.2 Control register 1, SSPCR1
The SSPCR1 register characteristics are:
Purpose The SSPCR1 is the control register 1 and contains four different bit
fields, that control various functions within the PrimeCell SSP.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 96.
Table 98 shows the bit assignments.
11.4.3 Data register, SSPDR
The SSPDR register characteristics are:
Purpose The SSPDR is the data register and is 16-bit wide. When the SSPDR
is read, the entry in the receive FIFO, pointed to by the current FIFO
read pointer, is accessed. As data values are removed by the
PrimeCell SSP receive logic from the incoming data frame, they are
placed into the entry in the receive FIFO, pointed to by the current
FIFO write pointer.
Table 98. SSPCR1 register bit assignments
Bits Name Function
[15:4] - RESERVED, read unpredictable, should be written as 0.
[3] SOD Slave-mode output disable. This bit is relevant only in the slave mode, MS = 1. In multiple-slave
systems, it is possible for a PrimeCell SSP master to broadcast a message to all slaves in the
system while ensuring that only one slave drives data onto its serial output line. In such systems
the RXD lines from multiple slaves could be tied together.
To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed
to drive the SSPTXD line:
0: SSP can drive the SSPTXD output in slave mode.
1: SSP must not drive the SSPTXD output in slave mode.
[2] MS Master or slave mode select.
This bit can be modified only when the PrimeCell SSP is disabled, SSE = 0:
0: device configured as master, default.
1: device configured as slave.
[1] SSE Synchronous serial port enable:
0: SSP operation disabled.
1: SSP operation enabled.
[0] LBM Loop back mode:
0: normal serial port operation enabled.
1: output of transmit serial shifter is connected to input of receive serial shifter internally.