Datasheet

SPI (serial peripheral interface) RM0352
102/138 DocID024647 Rev 1
11.4 SPI register descriptions
This section describes the PrimeCell SSP registers. Table 96 provides cross references to
individual registers.
11.4.1 Control register 0, SSPCR0
The SSPCR0 register characteristics are:
Purpose The SSPCR0 is a control register 0 and contains five bit fields that
control various functions within the PrimeCell SSP.
Usage constraints There are no usage constraints.
Configurations Available in all SSP configurations.
Attributes See Table 97.
SSP base + 0xFE8 SSPPeriphID2 RO 0x24 8
SSP base + 0xFEC SSPPeriphID3 RO 0x00 8
SSP base + 0xFF0 SSPPCellID0 RO 0x0D 8
PrimeCell identification registers,
SSPPCellID0-3 - see Section 11.4.11 on
page 111
SSP base + 0xFF4 SSPPCellID1 RO 0xF0 8
SSP base + 0xFF8 SSPPCellID2 RO 0x05 8
SSP base + 0xFFC SSPPCellID3 RO 0xB1 8
Table 96. PrimeCell SSP register summary (continued)
Offset Name Type Reset Width Description
Table 97. SSPCR0 register bit assignments
Bits Name Function
[15:8] SCR
Serial clock rate.
The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The
bit rate is:
F
SSPCLK
/ (CPSDVR x (1 + SCR))
where
CPSDVR is an even value from 2 to 254, programmed through the SSPCPSR register
and SCR is a value from 0 to 255.
[7] SPH SSPCLKOUT phase, applicable to Motorola SPI frame format only.
[6] SPO SSPCLKOUT polarity, applicable to Motorola SPI frame format only.