Datasheet

SPI (serial peripheral interface) RM0352

100/138 DocID024647 Rev 1

11 SPI (serial peripheral interface)

The SPI block is an IP provided by ARM (PL022 “PrimeCell

Synchronous Serial Port”).

Additional details about its functional blocks may be found in “ARM PrimeCell®

Synchronous Serial Port (PL022) Technical Reference Manual”.

11.1 Features

The SPI is a master or slave interface that enables synchronous serial communication with

slave or master peripherals having one of the following:

• A MOTOROLA SPI-compatible interface

• A TEXAS INSTRUMENTS synchronous serial interface

• A National Semiconductor MICROWIRE

interface.

The SPI interface operates as a master or slave interface. It supports bit rates up to 2 MHz

and higher in both master and slave configurations. The SPI has the following features:

• Parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep

transmit FIFO

• Serial-to-parallel conversion on received data, buffering it in a 16-bit wide, 8-location

deep receive FIFO

• Programmable data frame size from 4 to 16 bits

• Programmable clock bit rate and prescaler. The input clock may be divided by a factor

of 2 to 254 in steps of two to provide the serial output clock

• Programmable clock phase and polarity.

11.2 Clock prescaler

When configured as a master, an internal prescaler is used to provide the serial output

clock. The prescaler may be programmed through the SSPCPSR register to divide the

SSPCLK by a factor of 2 to 254 in steps of two. As least significant bit of the SSPCPSR

(equal mark space ratio) clock is generated.

The output of this prescaler is further divided by a factor 1 to 256, through the programming

of the SSPCR0 control register, to give a final master output clock.