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RM0352

Reference manual

Brain smart hub family

Introduction

This reference manual targets application developers. It provides complete information on

how to use the Brain smart hub microcontroller memory and peripherals.

The Brain is the first chip of smart hub microcontrollers family with different memory sizes,

packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

datasheet.

For information on the ARM

Cortex™-M0 core, please refer to the Cortex-M0 technical

reference manual.

Summary of content (138 pages)

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RM0352 Reference manual Brain smart hub family Introduction This reference manual targets application developers. It provides complete information on how to use the Brain smart hub microcontroller memory and peripherals. The Brain is the first chip of smart hub microcontrollers family with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the datasheet.
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Contents RM0352 Contents 1 Referenced document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . .
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RM0352 Contents 5.4 6 7 8 5.3.6 Lockup reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.7 Recall done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CRMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Description . . . . . . . . . . . . . . .
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Contents RM0352 8.2 8.3 9 8.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Programmer's model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.3.1 Summary of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.2 Register descriptions . . . . . . .
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RM0352 Contents 10.2.17 SMBUS slave control register (I2C_SMB_SCR) . . . . . . . . . . . . . . . . . . 95 10.2.18 I2C peripheral identification register 0 (I2C_PERIPHID0) . . . . . . . . . . . 96 10.2.19 I2C peripheral identification register 1 (I2C_PERIPHID1) . . . . . . . . . . . 96 10.2.20 I2C peripheral identification register 2 (I2C_PERIPHID2) . . . . . . . . . . . 97 10.2.21 I2C peripheral identification register 3 (I2C_PERIPHID3) . . . . . . . . . . . 97 10.2.
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Contents RM0352 12.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 12.4.1 UARTMSINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.4.2 UARTRXINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.4.3 UARTTXINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.4.4 UARTRTINTR . . . . . . . . . . . . . .
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RM0352 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97.
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RM0352 Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. List of tables SSPCPSR register bit assignments . . . . . . . . . . . . .
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List of figures RM0352 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 10/138 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset generation . . . . . . . . . . . . . . . . . .
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RM0352 1 Referenced document Referenced document Table 1.
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System and memory overview RM0352 2 System and memory overview 2.1 System architecture The main system consists of: • One master: – • Cortex-M0 core AHB bus Four slaves: – Internal 64 KByte SRAM for program or data with ECC referred as RAM bank0 – Internal 64 KByte SRAM for program or data referred as RAM bank1 – Internal 64 KByte Flash memory – AHB to APB, which connects all the APB peripherals These are interconnected using an AHB-Lite bus architecture as shown in Figure 1: Figure 1.
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RM0352 2.2 System and memory overview Memory organization Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant. The addressable memory space is divided into 16 main blocks, each of 256 MB.
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System and memory overview RM0352 Table 2.
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RM0352 System and memory overview Table 2. Memory table (continued) Address Cortex-M0 address map 0xE010_0000 - 0xEFFF_FFFF Size Remap = 0 Remap = 1 255 MBytes RESERVED (error response) 256 MBytes RESERVED (error response) Device 0xF000_0000 - 0xFFFF_FFFF 2.3 Embedded SRAM The Brain device features up to 128 KBytes of static SRAM (RAM bank0 + RAM bank1). It can be accessed as bytes, half words (16 bits) or full words (32 bits).
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System and memory overview 2.5 RM0352 Physical remap The application software can switch between two memory mappings (see Table 2: Memory table on page 14). This modification is performed by programming the REMAP bit in the Flash CONFIG register (see Section 6.3.5 on page 35). It can be used to switch the execution code from Flash to ECC RAM bank0. A typical use would be to copy the whole contents of the Flash into the RAM bank0 and then to set the REMAP bit.
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RM0352 3 Interrupts Interrupts Interrupts are handled by the Cortex-M0 “Nested Vector Interrupt controller” (NVIC). The NVIC controls specific Cortex-M0 interrupts (address 0x0 to 0x3C) as well as 32 user interrupts (address 0x40 to 0xBC). In the Brain device , user interrupts have been connected to the interrupt signals of the different peripherals (GPIO, Flash controller, timers UART, SPI, I2C, RAM bank0, WDG).
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Interrupts RM0352 Table 3.
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RM0352 4 GPIO GPIO The Brain device proposes 11 programmable I/Os. Each GPIO provides one programmable input or output that can be controlled in three modes: • GPIO Port mode: direction and data are programmed through registers (see Table 5: GPIO configuration registers) • Serial 0 and Serial 1 modes: the GPIO becomes a peripheral input or output line (see Table 4: GPIO alternate options) Each GPIO can generate an interrupt independently to the selected mode.
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GPIO RM0352 Table 5. GPIO configuration registers Address Bit Field name Reset R/W 0x00 14 GPIO_WDATA 14'h0000 R/W IO0 to IO10 output value 0x04 14 GPIO_DIR 14'h0000 R/W Data direction register (1 bit per GPIO): – 0: input – 1: output 0x08 14 GPIO_PE 14'h3FFF R/W Pull enable (1 bit per GPIO) – 0: pull disabled – 1: pull enabled 0x0C 32 R/W 2 bits mux selection for each I/Os: [1:0] conf. IO0; [3:2] conf. IO1, etc.
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RM0352 Clock and reset management unit 5 Clock and reset management unit 5.1 Introduction The Brain CRMU implements the clock and reset generation for the Brain device. The Brain CRMU is accessible through an APB interface. 5.2 Clock generation 5.2.1 General description The system clock can be selected from one of three clocks: Note: • 80 MHz RC oscillator clock • 32 kHz RC oscillator clock Real frequency is 32.768 kHz. However, it is called 32 kHz throughout the document to simplify.
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Clock and reset management unit RM0352 Figure 2. Clock generation FORFNBJDWHU HQ 5&B 0B5($'< 5&B 0B&/. FON 5&B .B&/. (;7B;2B(1 &508B&&5 > @ ;( ;2 FORFNBVZLWFK FON BLQ FORFNBVZLWFK FON BLQ FON BLQ FON BLQ VHO VHO +6B26&B6(/> @ &508B&&5 > @ 6<67(0B&/. +6B26&B6(/> @ &508B&&5 > @ (;7B;2B&/. 6<67(0B&/. 352&B',9)$&725 , &B&/. , & PDVWHU DQG VODYH FORFN IRU EDXG UDWH JHQHUDWLRQ FORFNBJDWHU HQ +&/.
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RM0352 5.2.2 Clock and reset management unit RC 80 MHz clock The 80 MHz clock is generated by an on-chip RC oscillator and is accurate to within 1 percent. 5.2.3 RC 32 kHz clock The 32 kHz clock is generated by an on-chip RC oscillator and is accurate to within 1 percent. 5.2.4 External clock The external clock is generated by a single ended clock source operating up to 80 MHz. 5.2.
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Clock and reset management unit 5.2.10 RM0352 SysTick clock The SysTick timer is clocked on the processor clock. 5.2.11 SPI clock The SPI IP has two clock inputs: one for the APB interface and one for the serial receive/transmit feature. Both are clocked with a clock synchronous to the processor clock. The serial clock can be divided by a factor of 2 to 254 by a step of two through the CPSDVSR field of the SSPCPSR register (see Table 101: SSPCPSR register bit assignments on page 107). 5.2.
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RM0352 Clock and reset management unit Figure 3. Reset generation 325 325(6(7Q '%*5(6(7Q WR WLPHUV &RUWH[ 0 GHEXJJHU %25 (&&B567B1 :'*B567B1 6<6B567B1 /2&.83B567B1 190B567B1 WR )ODVK FRQWUROOHU 5(&$//B'21( +5(6(7Q WR &RUWH[ 0 DQG $3% SHULSKHUDOV $0 5.3.2 Power-on reset The power-on reset signal is the combination of the POR signal and the BOR signal generated by the analog circuitry contained in the Brain device.
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Clock and reset management unit 5.3.5 RM0352 System reset request The system reset request is generated by the debug circuitry of the Cortex-M0. The debugger writes to the SYSRESETREQ bit of the “Application Interrupt and Reset Control Register” (AIRCR). The system reset request does not affect the debugger thus allowing the debugger to remain connected during the reset sequence. For more details on the CortexM0 system control and ID registers, refer to section B3.2.
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RM0352 5.4 Clock and reset management unit CRMU registers The CRMU registers are listed in Table 7 on page 27 and are described in details in the following pages. The base address of the CRMU block in the Brain memory map is 0xAB00_0000. Table 7. CRMU registers Address Name Type Reset value CRMU_BASE + 0x00 CRMU_RESET_REASON CRMU_BASE + 0x04 CRMU_CCR0 CRMU_BASE + 0x08 CRMU_CCR1 Indicates the cause of the last reset. See Table 8: CRMU_REASON_RESET on page 27.
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Clock and reset management unit RM0352 Table 9.
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RM0352 Clock and reset management unit 2. The field HS_OSC_SEL is programmed to select the clock output from the 3-way clock-switch. It is the root point for the processor clock. It can be programmed as per Table 12. Table 12. Processor clock root selection HS_OSC_SEL [7:6] Processor clock 00 80 MHz clock 01 32 KHz clock 10 External single ended clock 11 External single ended clock Table 13.
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Clock and reset management unit RM0352 Table 15. CRMU_ECCR0(1) Address Bit Field name Reset R/W Description 0 PRAM_SINGLE_ERR 1'b0 R ECC single error correction signal 1 PRAM_DOUBLE_ERR 1'b0 R ECC double error detection signal 7:2 PRAM_FAIL_BIT 6'b0 R ECC fail bit position provided after single error correction 15:8 RESERVED 8'b0 - - 31:16 PRAM_FAIL_ADDR 16'b0 R ECC fail address CRMU_BASE + 0x10 1. This register is cleared on read. Table 16.
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RM0352 Embedded Flash memory 6 Embedded Flash memory 6.1 Description The Flash array consists of 64 kBytes or 16 kWords (16384 x 32-bit) and is outside the Flash wrapper. The Flash can be accessed per 32-bit for read access and per 16-bit for write access. Erasing the whole Flash will result in all ones in every bit cell of the Flash. Note: For any erase or write action on the Flash, the system clock must be configured to use an internal oscillator.
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Embedded Flash memory RM0352 Table 18. Flash APB registers Address offset Name Width 0x00 COMMAND 8 RW(1) 0x0000_0000 Commands for the module. See Table 20: Flash command register on page 34. 0x04 CONFIG 2 RW(1) 0x0000_0049 Configure the wrapper. See Table 21: Flash CONFIG register on page 35. 0x08 IRQSTAT 5 RC(2) Flash status interrupts (masked). See Table 19: Flash interrupt register on page 32. 0x0C IRQMASK 5 RW(1) 0x0000_003F Mask for interrupts.
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RM0352 Embedded Flash memory Table 19. Flash interrupt register Bit Name Description 4 READOK Mass read was OK. 5 FLNREADY Flash not ready (sleep). The CMDDONE and CMDSTART bits are updated a few clock cycles after the requested command has been started by writing to the COMMAND register. Raw status The raw status register IRQRAW will always show the unmasked condition. Status The IRQSTAT register will show the masked version of the raw status register.
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Embedded Flash memory 6.3.4 RM0352 Command register Table 20. Flash command register Command Flash section Description Value Flash lock ERASE(1) Program memory Erase page defined by register ADDRESS. 0x11 Blocked MASSERASE(1) Program memory Mass erase (Flash is completely erased). 0x22 Allowed WRITE(1) Program memory Program one location (defined by registers DATA and ADDRESS). 0x33 Blocked MASSWRITE(1) Program memory Program all locations.
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RM0352 Embedded Flash memory The APB actions that need to be performed are: • Write ADDRESS register value of the word you want to write. • Write DATA register with the value you want to program. • Write PROGRAM command value to the COMMAND register. MASS WRITE One word can be programmed to every location in program memory. The APB actions that need to be performed are: • Write DATA register with the value you want to program. • Write MASS WRITE command value to the COMMAND register.
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Embedded Flash memory RM0352 Table 22. Flash 50 ns access time from specifications(1) FlashConfig[5:4] FlashConfig[0] = 0 (not registered) FlashConfig[0] = 1 (registered) 00 (0 wait states) 16 MHz (16 DMIPS) 20 MHz (14 DMIPS) 01 (1 wait states) 20 MHz (14 DMIPS) / 26 MHz (19 DMIPS) 40 MHz (22 DMIPS)(2) 10 (2 wait states) 40 MHz (22 DMIPS)(2) 40 MHz (16 DMIPS) Not functional 80 MHz 80 MHz (32 DMIPS) 11 (3 wait states) ® 1. DMIPS for Dhrystone MIPS . 2.
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RM0352 Embedded Flash memory Figure 4. Flash wrapper state machine operation 32:(5 3'0 5(&$// 5($' 5($'< 5($'< :5,7( (5$6( $0 6.5 Flash protection (ready state) After the recall, the 64-bit key stored in the Flash will be read by the Flash wrapper (one idle cycle between the two 32-bit reads). The Flash readout protection code is at the address 0x1001_FFF8 (this must match UNLOCKM register value) and 0x1001_FFFC (this must match UNLOCKL register value) of the Flash.
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Watchdog timer (WDG) 7 RM0352 Watchdog timer (WDG) The watchdog timer (WDG aka WDT) provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (WDOGINT), depending on a programmed value. The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. You can enable or disable the watchdog unit as required. The WDG is counting down at a fixed frequency of 32.768 kHz. 7.
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RM0352 Watchdog timer (WDG) disabled the watchdog counter is also stopped, and when the interrupt is enabled the counter will start from the programmed value, not the last count value. Write access to the registers within the watchdog timer can be disabled by the use of the watchdog lock register. Writing a value of 0x1ACC_E551 to this WDT_LOCK register allows write access to all other registers; writing any other value disables write access.
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Watchdog timer (WDG) RM0352 Table 26. WDG register list 40/138 Address Name Description WDG base + 0xFEC WDTPeriphID3 Peripheral identification register bits 31:24. See Section 7.2.8: Watchdog peripheral identification register WDTPeriphID0-3 on page 44. WDG base + 0xFF0 WDTPCellID0 Cell identification register bits 7:0. See Section 7.2.9: Watchdog PCell identification register WDTPCellID03 on page 45. WDG base + 0xFF4 WDTPCellID1 Cell identification register bits 15:8. See Section 7.2.
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RM0352 7.2.1 Watchdog timer (WDG) Watchdog load register (WDT_LR) The WDT_LR register is a 32-bit register containing the value from which the counter is to decrement. When this register is written to, the count is immediately re-started from the new value. The minimum valid value for WDT_LR is 0x1. Table 27.
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Watchdog timer (WDG) 7.2.3 RM0352 Watchdog control register WDT_CR The WDT_CR register allows configuring the watchdog timer. The bit assignment is listed in Table 32. Table 31. Watchdog control register WDT_CR WDT_CR (WDT Base + 0x008) Reset value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED 1 0 RESEN INTEN R R/W R/W Table 32. WDT_CR register bit fields Bit field Function Watchdog reset enable Enable watchdog reset output (WDOGRES).
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RM0352 7.2.5 Watchdog timer (WDG) Watchdog raw interrupt status register WDT_RIS The WDTRIS register is the raw interrupt status register. This value is ANDed with the interrupt enable bit from the control register to create the masked interrupt, which is passed to the interrupt output pin. Table 36 shows the bit assignment of the WDTRIS register. Table 35.
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Watchdog timer (WDG) 7.2.7 RM0352 Watchdog lock register WDT_LOCK Use of this register allows write access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 will enable write access to all other registers; writing any other value will disable write accesses.
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RM0352 Watchdog timer (WDG) Table 42. Watchdog peripheral identification register WDTPeriphID0-3 - part 2 WDTPeriphID1 (WDT Base + 0xFE4) Reset value: 0x0000_0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Designer0 Part number1 R R R Table 43.
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Watchdog timer (WDG) RM0352 Table 47. Watchdog PCell identification register WDTPCellID0-3 - part 2 WDTPCellID1 (WDT Base + 0xFF4) Reset value: 0x0000_00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED WDTPCellID1 R R 0 Table 48.
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ARM© dual timer module (SP804) RM0352 8 ARM© dual timer module (SP804) This section is intended for hardware and software engineers implementing “System-onChip” (SoC) designs. The SP804 timer is an IP provided by ARM (SP804). Additional details about its functional blocks may be found in “ARM Dual-Timer module (SP804) Technical Reference Manual”. 8.1 Introduction This section introduces the dual timer module (SP804). It contains the following parts: 8.1.
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ARM© dual timer module (SP804) RM0352 Figure 5 shows a simplified block diagram of the module. Figure 5. Simplified block diagram 7LPHU IUHH UXQQLQJ FRXQWHU 3UHVFDOHU ELW GRZQ FRXQWHU $0%$ $3% VLJQDOV $0%$ $3% LQWHUIDFH /RDG UHJLVWHU YDOXH 5HJLVWHU E DFNJURXQG ORDG 5HJLVWHU FRQWURO UHJ LVWHU 5DZ LQWHUUXSW VWDWXV UHJLVWHU 0DVNHG LQWHUUXSW VWDWXV UHJLVWHU ,QWHUUXSW FOHDU UHJLVWHU ,' UHJLVWHUV ,QWHJUDWLRQ WHVW UHJLVWHUV 7,0&/. 7,0&/.
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ARM© dual timer module (SP804) RM0352 The dual timer module consists of two identical programmable “Free Running Counters” (FRCs) that can be configured for 32-bit or 16-bit operation and one of three timer modes: • Free running • Periodic • One-shot. The FRCs operate from a common timer clock, TIMCLK with each FRC having its own clock enable input, TIMCLKEN1 and TIMCLKEN2. Each FRC also has a prescaler that can divide down the enabled TIMCLK rate by 1, 16, or 256.
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ARM© dual timer module (SP804) 8.2.2 RM0352 Functional description The dual timer module block diagram is shown in Figure 6. Figure 6. Dual timer module block diagram 7LPHU IUHH UXQQLQJ FRXQWHU 7LPHU /RDG UHJLVWHU 3UHVFDOHU 35(6(7Q 36(/ 3(1$%/( 3:5,7( 3$''5> @ 3:'$7$> @ 35'$7$> @ 3&/.
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ARM© dual timer module (SP804) RM0352 Free running counter blocks The two FRCs are identical and contain the 32/16-bit down counter and interrupt functionality. The counter logic is clocked independently of PCLK by TIMCLK in conjunction with a clock enable TIMCLKENX although there are constraints on the relationship between PCLK and TIMCLK. See Section : Clock signals and clock enables on page 51 for details of these constraints.
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ARM© dual timer module (SP804) RM0352 TIMCLK equals PCLK and TIMCLKENX equals one Figure 7 shows the case where TIMCLK is identical to PCLK and TIMCLKENX is permanently enabled. In this case, the counter is decremented on every TIMCLK edge. Figure 7. TIMCLK equals PCLK and TIMCLKENX equals one, clock example &RXQW Q Q Q 3&/. 7,0&/. 7,0&/.
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ARM© dual timer module (SP804) RM0352 Figure 9 shows how the timer clock enable is generated by the prescaler. Figure 9. Prescale clock enable generation 7LPHU FORFN HQDEOH 7,0&/.(1; 'LYLGH E\ 'LYLGH E\ 7LPHU FORFN HQDEOH DIWHU SUHVFDOLQJ 7LPHU; FRQWURO UHJLVWHU 7LPHU3UH> @ $0 Figure 10 shows an example of how the prescaler generates the timer clock enable for a prescaler setting of divide by 16. Figure 10.
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ARM© dual timer module (SP804) RM0352 Free running mode Free running mode is selected by setting the following bits in the TimerControl register: • Set TimerMode bit to 1 • Set OneShot bit to 0. The 32-bit or 16-bit counter operation is selected by setting the TimerSize bit appropriately in the TimerControl register.
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ARM© dual timer module (SP804) RM0352 new load value and uses this new load value for each subsequent reload for as long as the timer is enabled in periodic mode. If the counter is disabled by clearing the TimerEn bit in the TimerControl register, the counter halts and holds its current value. If the counter is re-enabled again then the counter continues decrementing from the current value. One-shot mode One-shot timer mode is selected by setting the OneShot bit in the TimerControl register to 1.
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ARM© dual timer module (SP804) RM0352 Figure 11 illustrates an example of the timing for an interrupt being raised and cleared. Figure 11. Example interrupt signal timing 3&/. 7,0&/. 7,0&/.
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ARM© dual timer module (SP804) 8.3.1 RM0352 Summary of registers A summary of the registers is provided in Table 52 and base address of each dual timer is listed below. The Timer0 base address is 0xA640_0000 The Timer1 base address is 0xA740_0000. The Timer2 base address is 0xA840_0000. The Timer3 base address is 0xA940_0000. The Timer4 base address is 0xA680_0000. The Timer5 base address is 0xA780_0000. The Timer6 base address is 0xA880_0000. The Timer7 base address is 0xA980_0000. Table 52.
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ARM© dual timer module (SP804) RM0352 Load register, TimerXLoad The TimerXLoad register is a 32-bit register that contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero. When this register is written to directly, the current count immediately resets to the new value at the next rising edge of TIMCLK which is enabled by TIMCLKENX. Note: The minimum valid value for TimerXLoad is 1.
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ARM© dual timer module (SP804) RM0352 Control register, TimerXControl The bit assignments of the control register are listed in Table 53. Table 53. Control register bit assignments Bits Name Type Function [31:8] - - [7] TimerEn Read/write Enable bit: 0 = timer module disabled (default) 1 = timer module enabled. RESERVED bits, do not modify, and ignore on read [6] TimerMode Read/write Mode bit: 0 = timer module is in free running mode (default) 1 = Timer module is in periodic mode.
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ARM© dual timer module (SP804) RM0352 Raw interrupt status register, TimerXRIS The TimerXRIS register indicates the raw interrupt status from the counter. The bit assignment is listed in Table 54. Table 54.
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ARM© dual timer module (SP804) RM0352 Figure 13 shows the bit assignments for the registers. Figure 13. Peripheral identification register bit assignment $POGJHVSBUJPO "DUVBM SFHJTUFS CJU BTTJHONFOU 3FWJTJPO 1BSU %FTJHOFS %FTJHOFS OVNCFS OVNCFS 1BSU OVNCFS $PODFQUVBM SFHJTUFS CJU BTTJHONFOU $POGJHVSBUJPO 3FWJTJPO OVNCFS %FTJHOFS 1BSU OVNCFS ".
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ARM© dual timer module (SP804) RM0352 Timer peripheral ID1 register, TimerPeriphID1 The TimerPeriphID1 register is hard-coded and the fields in the register determine the reset value.Table 58 lists the bit assignments of the register. Table 58.
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ARM© dual timer module (SP804) RM0352 PrimeCell ID2 register, TimerPCellID2 The TimerPCellID2 register is hard-coded and the fields in the register determine the reset value. Table 63 shows the bit assignment of the TimerPCellID2 register. Table 63.
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RM0352 System timer (SysTick) 9 System timer (SysTick) 9.1 About the SysTick The Brain device also includes a system timer (SysTick) that can be used by an operating system to ease porting from another platform. The SysTick can be polled by software or can be configured to generate an interrupt. The SysTick interrupt has its own entry in the vector table and therefore can have its own handler. For more details on SysTick system timer, see “ARMv6-M Architecture Reference Manual”. 9.
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System timer (SysTick) RM0352 9.3 SysTick registers descriptions 9.3.1 SysTick control and status register (SYST_CSR) Table 66.
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RM0352 System timer (SysTick) Type: R/W Reset: Description: SysTick reload value register [31:24] RESERVED [23:0] RELOAD: value to load into the SYST_CVR when the counter is enabled and when reaches zero. The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. Programming 0x00000000 has no effect because the SysTick exception request and COUNTFLAG are activated when counting down from 1 to 0.
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System timer (SysTick) Reset: RM0352 0x80000000 Description: SysTick calibration value register [31] NOREF: read as one indicates that no separate reference clock is provided. [30] SKEW: read as one indicates calibration value for the 10 ms inexact timing is not known. This may affect the suitability of the SysTick as a software realtime clock. [29:24] RESERVED [23:0] TENMS: contains the number of ticks to generate a 10 ms interval. Read as zero indicates calibration value is not known. 9.
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I2C bus interface RM0352 I2C bus interface 10 The Brain device provides two I2C bus interfaces that support following features: • Slave transmitter/receiver and master transmitter/receiver • 7- and 10-bit addressing • Standard (100 KHz) and fast (400 KHz) speeds • The transmit path is buffered in a 16-byte Tx FIFO and the receive paths is buffered in a 16-byte Rx FIFO.
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I2C bus interface RM0352 Table 70. I2C register list(1) (continued) Address Name Description I C masked interrupt status register. See Section 10.2.12: I2C masked interrupt status register (I2C_MISR) on page 92.
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I2C bus interface RM0352 10.2 I2C register descriptions 10.2.1 I2C control register (I2C_CR) Table 71.
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I2C bus interface RM0352 [25:20] FREQ: internal clock frequency (SMBUS) This field must be programmed to generate correct timings it is used to generate 1 MHZ in internal clock frequency. 000000: not allowed 000001: not allowed 000010: i2c_clk = 2 MHz (kernel clock) [19] NACK: not-acknowledge enable (SMBUS) In case of invalid data/command the software choose to cancel transfer by setting this bit to '1' or to continue reception.
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I2C bus interface RM0352 [9] RESERVED [8] FRX flushes the receive circuitry (FIFO, fsm). The configuration of the I2C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I2C clocks) and needs several system clock cycles before to be completed. On the completion, the I2C node (internal logic) clears this bit.
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I2C bus interface RM0352 [2:1] OM: Operating Mode. 00: Slave mode. The peripheral can only respond (transmit/receive) when addresses by a master device. 01: Master mode. The peripheral works in a multi-master system where itself cannot be addressed by another master device. It can only initiate a new transfer as master device. 10: Master/Slave mode. The peripheral works in a multi-master system where itself can be addressed by another master device, besides to initiate a transfer as a master device.
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I2C bus interface RM0352 I2C slave control register (I2C_SCR) 10.2.2 Table 72. I2C slave control register (I2C_SCR) I2C slave control register (I2C_SCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SLSU RESERVED ESA10 SA7 R/W R R/W R/W Address: I2CBaseAddress + 0x04 Type: R/W Reset: 0x000F0055 0 Description: I2C slave control register [31:16] SLSU: slave data setup time.
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I2C bus interface RM0352 Description: The control code word defines the features of the transfer. A typical transfer is defined from the following: • START condition • Start byte procedure (optional) • Address (7- or 10-bit) and read/write bit • Data transmission/reception. The master operations (read or write) are performed sequentially once at a time (no queuing mode). On the writing of the I2C_MCR register, the related operation is triggered.
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I2C bus interface RM0352 [10:8] EA10: extended address. Includes the extension (MSB bits) of the field A7 used to initiate the current transaction.Valid only when the addressing mode is set to 10 bits (AM = 10) [7:1] A7: Address. Includes the 7-bit address or the LSB bits of the10-bit address used to initiate the current transaction. [0] OP: operation 0: indicates a master write operation 1: indicates a master read operation 10.2.4 I2C transmit FIFO register (I2C_TFR) Table 74.
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I2C bus interface RM0352 I2C status register (I2C_SR) 10.2.5 Table 75.
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I2C bus interface RM0352 [20] SMBDEFAULT: SMBus device default address (slave mode) 0: no SMBus device default address 1: SMBus device default address received when ENARP = 1 • Cleared by hardware after a STOP condition or repeated START condition, or when PE = 0. [19:9] LENGTH: transfer length. For an MR, WTS operation the LENGTH field defines the actual size of the subsequent payload, in terms of number of bytes.
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I2C bus interface RM0352 [3:2] STATUS: controller status. Valid for the operations MW, MR, WTS, RFS. 0: NOP: no operation is in progress 1: ON_GOING: an operation is ongoing 10: OK: the operation (OP field) has been completed successfully 11: ABORT: the operation (OP field) has been aborted due to the occurrence of the event described in the CAUSE field.
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I2C bus interface RM0352 10.2.6 I2C receive FIFO register (I2C_RFR) Table 76. I2C receive FIFO register (I2C_RFR) I2C receive FIFO register (I2C_RFR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED RDATA R R Address: I2CBaseAddress + 0x18 Type: R Reset: 0x00000000 1 0 Description: I2C receive FIFO register [7:0] RDATA: receive data.
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I2C bus interface 10.2.7 RM0352 I2C transmit FIFO threshold register (I2C_TFTR) Table 77. I2C transmit FIFO threshold register (I2C_TFTR) I2C transmit FIFO threshold register (I2C_TFTR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED THRESHOLD_TX R R/W Address: I2CBaseAddress + 0x1C Type: R/W Reset: 0x00000000 0 Description: I2C transmit FIFO threshold register [9:0] THRESHOLD_TX: threshold Tx.
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I2C bus interface RM0352 10.2.9 I2C baud-rate counter register (I2C_BRCR) Table 79. I2C baud-rate counter register (I2C_BRCR) I2C baud-rate counter register (I2C_BRCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BRCNT2 R/W R/W Address: I2CBaseAddress + 0x28 Type: R/W Reset: 0x00000008 Description: [31:16] RESERVED [15:0] BRCNT2: baud rate counter 2.
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I2C bus interface RM0352 I2C interrupt mask set/clear register (I2C_IMSCR) 10.2.10 Table 80. I2C interrupt mask set/clear register (I2C_IMSCR) I2C interrupt mask set/clear register (I2C_IMSCR) R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ W W W W W W W W W W W Address: I2CBaseAddress + 0x2C Type: R/W Reset: 0x00000000 R 0 R/ R/ R/ R/ R/ R/ R/ W W W W W W W Description: I2C interrupt mask set/clear register [30] TIMEOUTM: Timeout or Tlow error mask. TIMEOUTM enables the interrupt bit.
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I2C bus interface RM0352 [23] SALM: slave arbitration lost mask. SALM enables the interrupt bit SAL. (SMBUS mode) 0: SAL interrupt is disabled. 1: SAL interrupt is enabled. [20] STDM: slave transaction done mask. STDM enables the interrupt bit STD. 0: STD interrupt is disabled. 1: STD interrupt is enabled. [19] MTDM: master transaction done mask. MTDM enables the interrupt bit MTD. 0: MTD interrupt is disabled. 1: MTD interrupt is enabled. [18] WTSRM: write-to-slave request mask.
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I2C bus interface RM0352 [3] TXFOVRM: Tx FIFO overrun mask. TXFOVRM enables the interrupt bit TFXOVR. 0: TXFOVR interrupt is disabled. 1: TXFOVR interrupt is enabled. [2] TXFFM: Tx FIFO full mask. TXFFM enables the interrupt bit TXFF. 1: TXFF interrupt is enabled. 0: TXFF interrupt is disabled. [1] TXFNEM: Tx FIFO nearly empty mask. TXFNEM enables the interrupt bit TXFNE. 0: TXFNE interrupt is disabled. 1: TXFNE interrupt is enabled. [0] TXFEM: Tx FIFO empty mask. TXFEM enables the interrupt bit TXFE.
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I2C bus interface RM0352 • • • When set in slave mode: slave resets the communication and lines are released by hardware. When set in master mode: STOP condition sent by hardware. Cleared by software writing in I2C_ICR, or by hardware when I2C_CR: PE = 0. [29] PECERR: PEC error in reception (SMBUS mode) 0: no PEC error: receiver returns ACK after PEC reception (if I2C_CR:NACK = 0). 1: PEC error: receiver returns NACK after PEC reception (whatever I2C_CR: NACK).
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I2C bus interface RM0352 1: master arbitration lost. [23] SAL: slave arbitration lost (SMBUS mode). SAL is set when the slave loses the arbitration during the data phase. A collision occurs when 2 devices transmit simultaneously 2 opposite values on the serial dataline. The device that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, releases the bus and waits for the idle state (STOP condition received) on the bus line.
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I2C bus interface RM0352 0: Tx FIFO is not empty. 1: Tx FIFO is empty with the read-from-slave operation in progress. [16] RFSR: read-from-slave request. RFSR is set when a read-from-slave “slavetransmitter” request is received (I2C slave is addressed) from the I2C line. On the assertion of this interrupt the Tx FIFO is flushed (pending data are cleared) and the CPU shall put the data in the Tx FIFO. This bit is self-cleared writing data in the FIFO.
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I2C bus interface RM0352 [3] TXFOVR: Tx FIFO overrun. TXFOVR is set when a write operation in the Tx FIFO is performed and the Tx FIFO is full. The application must avoid overflow condition by a proper data flow control. Anyway in case of overrun, the application shall flush the transmitter (I2C_CR:FTX bit to set) because the Tx FIFO content is corrupted (at least a word has been lost in the FIFO). This interrupt is cleared setting the related bit of the I2C_ICR register.
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I2C bus interface RM0352 Description: The I2CMISR register indicates the interrupt sources after masking. For the description of each single bit, refer to the register I2C_RISR. The output signal int_gbl is asserted when at least one interrupt source of this register is pending. I2C interrupt clear register (I2C_ICR) 10.2.13 Table 83.
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I2C bus interface RM0352 [8:0] I2C_THDDAT: hold time data value In master or slave mode, when the I2C controller detect a failing edge in SCL line, the counter, which is loaded by the I2C_THDDAT, is launched. Once the I2C_THDDAT value is reached, the data is transferred. The reset value is valid only when I2C frequency equal to 48 MHz. If frequency changes the user must program the register and this value must be greater than 4. Note: To set the timing register we use Equation 3.
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I2C bus interface RM0352 10.2.16 I2C setup time START condition F/S (I2C_TSUSTA_FST_STD) Table 86.
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I2C bus interface RM0352 [7:1] DSA7: slave address in dual addressing mode. [0] DUAL: dual addressing mode enable. 0: only SA7 is recognized in 7-bit addressing mode. 1: both SA7 and DSA7 are recognized in 7-bit addressing mode. 10.2.18 I2C peripheral identification register 0 (I2C_PERIPHID0) Table 88.
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I2C bus interface RM0352 10.2.20 I2C peripheral identification register 2 (I2C_PERIPHID2) Table 90. I2C peripheral identification register 2 (I2C_PERIPHID2) I2C peripheral identification register 2 (I2C_PERIPHID2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RESERVED 4 3 2 1 REVISION DESIGNER1 R R Address: I2CBaseAddress + 0xFE8 Type: R Reset: 0x00000038 0 R Description: I2C peripheral identification register 2. [7:4] REVISION: these bits read back as 0x3.
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I2C bus interface 10.2.22 RM0352 I2C PCell identification register 0 (I2C_PCELLID0) Table 92. I2C PCell identification register 0 (I2C_PCELLID0) I2C PCell identification register 0 (I2C_PCELLID0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED I2CPCELLID0 R R Address: I2CBaseAddress + 0xFF0 Type: R Reset: 0x0000000D 0 Description: The I2C_PCELLID0-3 registers are four 8-bit registers, that span address location 0xFF0 to 0xFFC.
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I2C bus interface RM0352 10.2.24 I2C PCell identification register 2 (I2C_PCELLID2) Table 94. I2C PCell identification register 2 (I2C_PCELLID2) I2C PCell identification register 2 (I2C_PCELLID2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED I2CPCELLID2 R R Address: I2CBaseAddress + 0xFF8 Type: R Reset: 0x00000005 Description: I2C PCell identification register 2. [7:0] I2CPCELLID2: These bits read back as 0x05. 10.2.
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SPI (serial peripheral interface) 11 RM0352 SPI (serial peripheral interface) The SPI block is an IP provided by ARM (PL022 “PrimeCell® Synchronous Serial Port”). Additional details about its functional blocks may be found in “ARM PrimeCell® Synchronous Serial Port (PL022) Technical Reference Manual”. 11.
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RM0352 11.3 SPI (serial peripheral interface) SPI registers The SPI has following programmable parameters: • Master or slave mode • Enabling of operation • Frame format • Communication baud rate • Clock phase and polarity • Data widths from 4 to 16 bits wide • Interrupt masking. The SPI base address block in the Brain memory map is 0xA300_0000. Table 96 shows the PrimeCell SSP registers. Table 96.
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SPI (serial peripheral interface) RM0352 Table 96. PrimeCell SSP register summary (continued) Offset Name Type Reset Width SSP base + 0xFE8 SSPPeriphID2 RO 0x24 8 SSP base + 0xFEC SSPPeriphID3 RO 0x00 8 SSP base + 0xFF0 SSPPCellID0 RO 0x0D 8 SSP base + 0xFF4 SSPPCellID1 RO 0xF0 8 SSP base + 0xFF8 SSPPCellID2 RO 0x05 8 SSP base + 0xFFC SSPPCellID3 RO 0xB1 8 11.4 Description PrimeCell identification registers, SSPPCellID0-3 - see Section 11.4.
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RM0352 SPI (serial peripheral interface) Table 97. SSPCR0 register bit assignments (continued) Bits Name Function [5:4] FRF Frame format: 00: Motorola SPI frame format 01: TI synchronous serial frame format 10: National Semiconductor Microwire frame format 11: reserved, undefined operation.
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SPI (serial peripheral interface) 11.4.2 RM0352 Control register 1, SSPCR1 The SSPCR1 register characteristics are: Purpose The SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 96. Table 98 shows the bit assignments. Table 98.
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RM0352 SPI (serial peripheral interface) When the SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must rightjustify data written to the transmit FIFO.
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SPI (serial peripheral interface) RM0352 Table 100 shows the bit assignments. Table 100. SSPSR register bit assignments Bits Name [15:5] - [4] BSY Function RESERVED, read unpredictable, should be written as 0. PrimeCell SSP busy flag, RO: 0: SSP is idle. 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [3] RFF Receive FIFO full, RO: 0: receive FIFO is not full. 1: receive FIFO is full. [2] RNE Receive FIFO not empty, RO: 0: receive FIFO is empty.
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RM0352 SPI (serial peripheral interface) Table 101 shows the bit assignments. Table 101. SSPCPSR register bit assignments Bits Name [15:8] - [7:0] CPSDVSR 11.4.6 Function RESERVED, read unpredictable, must be written as 0. Clock prescale divisor. Must be an even number from 2 - 254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
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SPI (serial peripheral interface) 11.4.7 RM0352 Raw interrupt status register, SSPRIS The SSPRIS register characteristics are: Purpose The SSPRIS register is the raw interrupt status register. It is an RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 96 on page 101.
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RM0352 11.4.9 SPI (serial peripheral interface) Interrupt clear register, SSPICR The SSPICR register characteristics are: Purpose The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 96 on page 101. Table 105 shows the bit assignment. Table 105.
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SPI (serial peripheral interface) RM0352 The following subsections describe the four 8-bit peripheral identification registers: • SSPPeriphID0 register • SSPPeriphID1 register • SSPPeriphID2 register • SSPPeriphID3 register SSPPeriphID0 register The SSPPeriphID0 register characteristics are: Purpose The SSPPeriphID0 register is hard-coded and the fields within the register determine the reset value. Usage constraints There are no usage constraints.
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RM0352 SPI (serial peripheral interface) Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 96 on page 101. Table 108 shows the bit assignments. Table 108.
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SPI (serial peripheral interface) RM0352 The following subsections describe the four, 8-bit PrimeCell identification registers: • SSPPCellID0 register • SSPPCellID1 register • SSPPCellID2 register • SSPPCellID3 register SSPPCellID0 register The SSPPCellID0 register characteristics are: Purpose The SSPPCellID0 register is hard-coded and the fields within the register determine the reset value. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations.
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RM0352 SPI (serial peripheral interface) Configurations Available in all SSP configurations. Attributes See Table 96 on page 101. Table 112 shows the bit assignments. Table 112.
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SPI (serial peripheral interface) RM0352 Provision of the individual outputs in addition to a combined interrupt output, enables the use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic data flow interrupts SSPTXINTR and SSPRXINTR have been separated from the status interrupts, so that data can be read or written in response to only the FIFO trigger levels.
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RM0352 12 UART (universal asynchronous receive transmit) UART (universal asynchronous receive transmit) The Brain device has one asynchronous serial ports (UART). The UART block is an IP provided by ARM (PL011). Additional details about its functional blocks can be found in “PrimeCell®UART(PL011) Technical Reference Manual”. 12.
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UART (universal asynchronous receive transmit) 12.2 RM0352 IrDA SIR block The IrDA “Serial InfraRed” (SIR) block contains an IrDA SIR protocol ENDEC. The SIR protocol ENDEC can be enabled for serial communication through signals nSIROUT and SIRIN to an infrared transducer instead of using the UART signals UARTTXD and UARTRXD. If the SIR protocol ENDEC is enabled, the UARTTXD line is held in the passive state (HIGH) and transitions of the modem status, or the UARTRXD line have no effect.
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RM0352 UART (universal asynchronous receive transmit) The transmit and receive data flow interrupts UARTRXINTR and UARTTXINTR have been separated from the status interrupts. This enables use of the UARTRXINTR and UARTTXINTR so that data can be read or written in response to the FIFO trigger levels. The error interrupt, UARTEINTR, can be triggered when there is an error in the reception of data. A number of error conditions are possible.
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UART (universal asynchronous receive transmit) RM0352 To update the transmit FIFO you must: • Write data to the transmit FIFO, either prior to enabling the UART and the interrupts, or after enabling the UART and interrupts. Note: The transmit interrupt is based on a transition through a level, rather than on the level itself. When the interrupt and the UART is enabled before any data is written to the transmit FIFO the interrupt is not set.
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RM0352 UART (universal asynchronous receive transmit) Table 114. UART register summary Offset Name 0x000 UARTDR 0x004 UARTRSR / UARTECR 0x008-0x014 0x018 UARTFR 0x01C Type Reset Width Description RW 0x-- 12/8 Data register, UARTDR - see Section 12.6.1 on page 120 RW 0x00 4/0 Receive status register/error clear register, UARTRSR/UARTECR - see Section 12.6.2 on page 121 RW 0x00 6 RESERVED RO 9'b10010-- 9 Flag register, UARTFR - see Section 12.6.
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UART (universal asynchronous receive transmit) RM0352 Table 114.
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RM0352 UART (universal asynchronous receive transmit) Table 115. UARTDR register(1) Bits Name 15:12 - 11 OE Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. 10 BE Break error.
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UART (universal asynchronous receive transmit) RM0352 Table 116. UARTRSR/UARTECR register(1) (continued) Bits Name Function 2 BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In the FIFO mode, this error is associated with the character at the top of the FIFO.
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RM0352 UART (universal asynchronous receive transmit) Table 117. UARTFR register (continued) Bits Name Function 5 TXFF Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. 4 RXFE Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H register.
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UART (universal asynchronous receive transmit) 12.6.5 RM0352 Integer baud rate register, UARTIBRD The UARTIBRD register is the integer part of the baud rate divisor value. Table 119 lists the register bit assignments. Table 119. UARTIBRD register Bits Name Function 15:0 BAUD DIVINT 12.6.6 The integer baud rate divisor. These bits are cleared to 0 on reset. Fractional baud rate register, UARTFBRD The UARTFBRD register is the fractional part of the baud rate divisor value.
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RM0352 UART (universal asynchronous receive transmit) The maximum error using a 6-bit UARTFBRD register = 1/64 × 100 = 1.56%. This occurs when m = 1, and the error is cumulative over 64 clock ticks. Table 121 lists some typical bit rates and their corresponding divisors when UARTCLK is 7.3728MHz. These values do not use the fractional divider so the value in the UARTFBRD register is zero. Table 121. Typical baud rates and integer divisors when UARTCLK = 7.
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UART (universal asynchronous receive transmit) 12.6.7 RM0352 Line control register, UARTLCR_H The UARTLCR_H register is the line control register. This register accesses bits 29 to 22 of the UART line control register, UARTLCR. All the bits are cleared to 0 when reset. Table 123 lists the register bit assignments. Table 123. UARTLCR_H register Bits Name 15:8 - 7 SPS 6:5 Function RESERVED, do not modify, read as zero. Stick parity select.
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RM0352 Note: UART (universal asynchronous receive transmit) To update the three registers there are two possible sequences: • UARTIBRD write, UARTFBRD write, and UARTLCR_H write • UARTFBRD write, UARTIBRD write, and UARTLCR_H write. To update UARTIBRD or UARTFBRD only: • UARTIBRD write, or UARTFBRD write, and UARTLCR_H write.
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UART (universal asynchronous receive transmit) RM0352 Table 125. UARTCR register (continued) Bits Name 10 DTR Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to 1 then nUARTDTR is LOW. 9 RXE Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.
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RM0352 UART (universal asynchronous receive transmit) Program the control registers as follows: 12.6.9 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by setting the FEN bit to 0 in the line control register, UARTLCR_H in Section 12.6.7 on page 126. 4. Reprogram the UARTCR register. 5. Enable the UART. Interrupt FIFO level select register, UARTIFLS The UARTIFLS register is the interrupt FIFO level select register.
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UART (universal asynchronous receive transmit) 12.6.10 RM0352 Interrupt mask set/clear register, UARTIMSC The UARTIMSC register is the interrupt mask set/clear register. It is a read/write register. On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. Table 127 lists the register bit assignments.
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RM0352 UART (universal asynchronous receive transmit) 12.6.11 Raw interrupt status register, UARTRIS The UARTRIS register is the raw interrupt status register. It is a read-only register. This register returns the current raw status value, prior to masking, of the corresponding interrupt. A write has no effect. Caution: All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status interrupt bits are undefined after reset.
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UART (universal asynchronous receive transmit) 12.6.12 RM0352 Masked interrupt status register, UARTMIS The UARTMIS register is the masked interrupt status register. It is a read-only register. This register returns the current masked status value of the corresponding interrupt. A write has no effect. All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. Table 129 lists the register bit assignments.
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RM0352 12.6.13 UART (universal asynchronous receive transmit) Interrupt clear register, UARTICR The UARTICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Table 130 lists the register bit assignments. Table 130. UARTICR register Bits 15:11 Name Function RESERVED RESERVED, read as zero, do not modify. 10 OEIC Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
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UART (universal asynchronous receive transmit) RM0352 UARTPeriphID0 register The UARTPeriphID0 register is hard coded and the fields in the register determine the reset value. Table 131 lists the register bit assignments. Table 131. UARTPeriphID0 register Bits Name 15:8 - 7:0 Description RESERVED, read undefined must read as zeros. PartNumber0 These bits read back as 0x11. UARTPeriphID1 register The UARTPeriphID1 register is hard coded and the fields in the register determine the reset value.
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RM0352 UART (universal asynchronous receive transmit) UARTPeriphID3 register The UARTPeriphID3 register is hard coded and the fields in the register determine the reset value. Table 134 lists the register bit assignments. Table 134. UARTPeriphID3 register Bits Name 15:8 - 7:0 12.6.15 Description RESERVED, read undefined, must read as zeros. Configuration These bits read back as 0x00.
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UART (universal asynchronous receive transmit) RM0352 UARTPCellID2 register The UARTPCellID2 register is hard coded and the fields in the register determine the reset value. Table 137 lists the register bit assignments. Table 137. UARTPCellID2 register Bits Name 15:8 - 7:0 UARTPCellID2 Description RESERVED, read undefined, must read as zeros. These bits read back as 0x05. UARTPCellID3 register The UARTPCellID3 register is hard coded and the fields in the register determine the reset value.
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RM0352 13 Revision history Revision history Table 139. Document revision history Date Revision 06-Feb-2014 1 Changes Initial release.
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RM0352 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.