User guide

Embedded Trace Macrocell

ID072410 Non-Confidential

Table 10-7 ETMCR bit assignments

Bits Name Function

[31:22] - RAZ

[28] Timestamp enable When set, this bit enables timestamping.

An ETM reset sets this bit to 0.

[21] Port size[3] This bit is implemented but has no function.

An ETM reset sets this bit to 0.

[20:18] - Reserved

[17:16] Port mode [1:0] These bits are implemented but have no function.

An ETM reset sets these bits to 0.

[15:14] - Reserved

[13] Port mode[2] This bit is implemented but has no function.

An ETM reset sets this bit to 0.

[12] - Reserved

[11] ETM port selection This bit can be used to control other trace components in an implementation. The possible values

are:

0 ETMEN is LOW.

1 ETMEN is HIGH.

This bit must be set by the trace software tools to ensure that trace output is enabled from this

ETM.

An ETM reset sets this bit to 0.

[10] ETM programming This bit must be set to 1 at the start of the ETM programming sequence. Tracing is prevented while

this bit is set to 1.

On an ETM reset this bit is set to

0b1

[9] Debug request control When set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is

observed. This enables the ARM processor to be forced into Debug state.

An ETM reset sets this bit to 0.

[8] Branch output When set to 1 all branch addresses are output, even if the branch was because of a direct branch

instruction. Setting this bit enables reconstruction of the program flow without having access to

the memory image of the code being executed.

When this bit is set to 1, more trace data is generated, and this may affect the performance of the

trace system. Information about the execution of a branch is traced regardless of the state of this

bit.

An ETM reset sets this bit to 0.

[7] Stall processor The FIFOFULL output can be used to stall the processor to prevent overflow. The FIFOFULL

output is only enabled when the stall processor bit is set to 1. When the bit is 0 the FIFOFULL

output remains LOW at all times and the FIFO overflows if there are too many trace packets. Trace

resumes without corruption once the FIFO has drained, if overflow does occur.

An ETM reset sets this bit to 0.

For information about the interaction of this bit with the ETMFFLR register see the Embedded

Trace Macrocell Architecture Specification.