User guide

Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-9
ID072410 Non-Confidential
10.3 ETM Programmers model
This section describes the mechanisms for programming the registers used to set up the trace
and triggering facilities of the macrocell. The programmers model enables you to use the ETM
registers to control the macrocell.
10.3.1 Modes of operation and execution
ETM-M3 implements ETMv3.5 for tracing 16-bit and 32-bit Thumb instructions. The
Embedded Trace Macrocell Architecture Specification describes the features of ETMv3.5.
See Features on page 10-2 for information on the trace features of the ETM-M3.
When the ETM is powered up or reset, you must program all of the registers that do not have an
architected reset state before you enable tracing. If you do not do so, the trace results are
Unpredictable.
When programming the ETM registers you must enable all the changes at the same time. To
achieve this, the Programming bit in ETMCR should be used. See Main Control Register,
ETMCR on page 10-11.
When the Programming bit is set to 0 you must not write to registers other than ETMCR,
because this can lead to Unpredictable behavior.
When setting the Programming bit, you must not change any other bits of ETMCR. You must
only change the value of bits other than the Programming bit of ETMCR when bit [1] of ETMSR
is set to 1. ARM recommends that you use a read-modify-write procedure when changing
ETMCR.
10.3.2 Register summary
Table 10-6 shows the ETM registers.
Table 10-6 ETM registers
Address Name Reset Type Description
0xE0041000 ETMCR 0x00000411 RW Main Control Register, ETMCR on page 10-11
0xE0041004 ETMCCR 0x8C802000 RO Configuration Code Register, ETMCCR on page 10-14
0xE0041008 ETMTRIGGER - RW Trigger Event Register.
See ARM Embedded Trace Macrocell Architecture Specification
0xE0041010 ETMSR - RW
ETM Status Register. See ARM Embedded Trace Macrocell
Architecture Specification
0xE0041014 ETMSCR
0x00020D09
RO System Configuration Register, ETMSCR on page 10-15
0xE0041020 ETMTEEVR - RW
TraceEnable Event Register. See ARM Embedded Trace Macrocell
Architecture Specification
0xE0041024 ETMTECR1 - RW TraceEnable Control 1 Register, ETMTECR1 on page 10-16
0xE0041028 ETMFFLR - RW
FIFOFULL Level Register. See ARM Embedded Trace Macrocell
Architecture Specification
0xE0041140 ETMCNTRLDVR1 - RW Free-running counter reload value
0xE00411E0 ETMSYNCFR 0x00000400 RO
Synchronisation Frequency Register. See ARM Embedded Trace
Macrocell Architecture Specification