User guide

Embedded Trace Macrocell

ID072410 Non-Confidential

10.1 About the ETM

The ETM is an optional debug component that enables reconstruction of program execution.

The ETM is designed to be a high-speed, low-power debug tool that only supports instruction

trace. This ensures that area is minimized, and that gate count is reduced.

The ETM implements ARM ETM architecture v3.5. See the ARM Embedded Trace Macrocell

Architecture Specification.

The ETM traces all 32-bit Thumb instructions as a single instruction. The ETM traces

instructions following an

instruction as normal conditional instructions. The decompressor

does not need to refer to the

instruction.

You can use the CoreSight ETM-M3 either with the Cortex-M3 Trace Port Interface Unit

(M3-TPIU), or as part of a CoreSight system.

10.1.1 Features

ETM-M3 provides:

• tracing of 16-bit and 32-bit Thumb instructions

• four EmbeddedICE watchpoint inputs

• a Trace Start/Stop block with EmbeddedICE inputs

• two external inputs

• a 24-byte FIFO queue

• global timestamping.

See the Embedded Trace Macrocell Architecture Specification for information about:

• the trace protocol

• controlling tracing using triggering and filtering resources.

See the Cortex-M3 Integration and Implementation Manual for information about the macrocell

signals.

10.1.2 Configurable options

The ETM-M3 macrocell includes the following configuration inputs:

• the maximum number of external inputs, see External inputs on page 10-6

• whether the system supports the FIFOFULL mechanism for stalling the processor, see

Table 10-1 on page 10-4.