User guide

Debug
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 7-8
ID072410 Non-Confidential
[5:4] AddrInc Auto address increment and pack mode on Read or Write data access. Only
increments if the current transaction completes with no error.
Auto address incrementing and packed transfers are not performed on
access to Banked Data registers
0x10 - 0x1C . The status of these bits is
ignored in these cases.
Increments and wraps within a 4-KB address boundary, for example from
0x1000 to 0x1FFC . If the start is at 0x14A0 , then the counter increments to
0x1FFC , wraps to 0x1000 , then continues incrementing to 0x149C .
0b00 = auto increment off.
0b01 = increment single. Single transfer from corresponding byte lane.
0b10 = increment packed.
b
0b11 = reserved. No transfer.
Size of address increment is defined by the Size field [2:0].
Reset value:
0b00 .
[3] - Reserved.
[2:0] Size Size of access field:
0b000 = 8 bits
0b001 = 16 bits
0b010 = 32 bits
0b011 - 111 are reserved.
Reset value:
0b000 .
a. When clear, this bit prevents the debugger from setting the C_DEBUGEN bit in the Debug Halting
Control and Status Register, and so prevents the debugger from being able to halt the processor.
b. See the definition of packed transfers in the ARM Debug Interface v5 Architecture Specification.
Table 7-6 CSW bit assignments (continued)
Bits Name Function