User guide

Debug
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 7-7
ID072410 Non-Confidential
Configurations This register is available in all processor configurations.
Attributes See the register summary in Table 7-5 on page 7-6.
Figure 7-2 shows the CSW bit assignments.
Figure 7-2 CSW bit assignments
Table 7-6 shows the CSW bit assignments.
11 831 29 28 2630 12 7 6 5 4 3 2 0
Mode
Reserved Size
25 24
TransInProg
DbgStatus
AddrInc
Hprot1
MasterType
Reserved
Reserved Reserved
Table 7-6 CSW bit assignments
Bits Name Function
[31:30] - Reserved. Read as
0b00 .
[29]
MasterType
a
0 = core.
1 = debug.
This bit must not be changed if a transaction is outstanding. A debugger
must first check bit [7], TransInProg.
Reset value =
0b1 .
An implementation can configure this bit to be read only with a value of 1.
In that case, transactions are always indicated as debug.
[28:26] - Reserved, 0b000 .
[25] Hprot1 User and Privilege control - HPROT[1].
Reset value =
0b1 .
[24] - Reserved,
0b1 .
[23:12] - Reserved,
0x000 .
[11:8] Mode Mode of operation bits:
0b0000 = normal download and upload mode
0b0001 - 0b1111 are reserved.
Reset value =
0b0000 .
[7] TransInProg Transfer in progress. This field indicates if a transfer is in progress on the
APB master port.
[6] DbgStatus Indicates the status of the DAPEN port.
1 = AHB transfers permitted.
0 = AHB transfers not permitted.