User guide

Debug
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SCS CoreSight identification
Table 7-3 shows the SCS CoreSight identification registers and values for debugger detection.
Final debugger identification of the Cortex-M3 processor is through the CPUID register in the
SCS. See CPUID Base Register, CPUID on page 4-5.
See the ARMv7-M Architectural Reference Manual and the ARM CoreSight Components
Technical Reference Manual for more information about the SCS CoreSight identification
registers, and their addresses and access types.
7.1.3 Debug register summary
Table 7-4 shows the debug registers. Each of these registers is 32 bits wide and is described in
the ARMv7-M Architectural Reference Manual.
Core debug is an optional component. If core debug is removed then halt mode debugging is not
supported, and there is no halt, stepping, or register transfer functionality. Debug monitor mode
is still supported.
Table 7-3 SCS identification values
Address Register Value Description
0xE000EFD0 Peripheral ID4 0x00000004 Component and Peripheral ID register formats in
the ARMv7-M Architectural Reference Manual.
0xE000EFE0 Peripheral ID0 0x00000000
0xE000EFE4
Peripheral ID1 0x000000B0
0xE000EFE8
Peripheral ID2 0x0000000B
0xE000EFEC
Peripheral ID3 0x00000000
0xE000EFF0
Component ID0 0x0000000D
0xE000EFF4
Component ID1 0x000000E0
0xE000EFF8
Component ID2 0x00000005
0xE000EFFC
Component ID3 0x000000B1
Table 7-4 Debug registers
Address Name Type Reset Description
0xE000ED30 DFSR RW
0x00000000
a
a. Power-on reset only
Debug Fault Status Register
0xE000EDF0 DHCSR RW 0x00000000 Debug Halting Control and Status Register
0xE000EDF4 DCRSR WO - Debug Core Register Selector Register
0xE000EDF8 DCRDR RW - Debug Core Register Data Register
0xE000EDFC DEMCR RW 0x00000000 Debug Exception and Monitor Control Register