User guide

Debug

ID072410 Non-Confidential

7.1 About debug

The processor implementation determines the debug configuration, including whether debug is

implemented. If the processor does not implement debug, no ROM table is present and the halt,

breakpoint, and watchpoint functionality is not present.

Basic debug functionality includes processor halt, single-step, processor core register access,

Vector Catch, unlimited software breakpoints, and full system memory access. See the

ARMv7-M Architectural Reference Manual for more information.

The debug option might include:

• a breakpoint unit supporting two literal comparators and six instruction comparators, or

only two instruction comparators

• a watchpoint unit supporting one or four watchpoints.

For processors that implement debug, ARM recommends that a debugger identify and connect

to the debug components using the CoreSight debug infrastructure.

Figure 7-1 shows the recommended flow that a debugger can follow to discover the components

in the CoreSight debug infrastructure. In this case a debugger reads the peripheral and

component ID registers for each CoreSight component in the CoreSight system.

Figure 7-1 CoreSight discovery

To identify the Cortex-M3 processor within the CoreSight system, ARM recommends that a

debugger perform the following actions:

1. Locate and identify the Cortex-M3 ROM table using its CoreSight identification. See

Table 7-1 on page 7-3 for more information.

CoreSight debug port

Cortex-M3 ROM table

CoreSight ID

Pointers

CoreSight access port

Base pointer

System control space

CoreSight ID

Cortex-M3 CPUID

Debug control

‡ Data watchpoint unit

CoreSight ID

Watchpoint control

‡ Optional component

Redirection from the

‡ System ROM table, if implemented

‡ Breakpoint unit

CoreSight ID

Breakpoint control