User guide

Nested Vectored Interrupt Controller
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 6-4
ID072410 Non-Confidential
6.3 NVIC programmers model
Table 6-1 shows the NVIC registers.
The following sections describe the NVIC registers whose implementation is specific to this
processor. Other registers are described in the ARMv7M Architecture Reference Manual.
6.3.1 Interrupt Controller Type Register, ICTR
The ICTR characteristics are:
Purpose Shows the number of interrupt lines that the NVIC supports.
Usage Constraints There are no usage constraints.
Configurations This register is available in all processor configurations.
Attributes See the register summary in Table 6-1.
Figure 6-1 shows the ICTR bit assignments.
Figure 6-1 ICTR bit assignments
Table 6-1 NVIC registers
Address Name Type Reset Description
0xE000E004 ICTR RO - Interrupt Controller Type Register, ICTR
0xE000E100 -
0xE000E11C
NVIC_ISER0 -
NVIC_ISER7
RW 0x00000000 Interrupt Set-Enable Registers
0xE000E180 -
0E000xE19C
NVIC_ICER0 -
NVIC_ICER7
RW 0x00000000 Interrupt Clear-Enable Registers
0xE000E200 -
0xE000E21C
NVIC_ISPR0 -
NVIC_ISPR7
RW 0x00000000 Interrupt Set-Pending Registers
0xE000E280 -
0xE000E29C
NVIC_ICPR0 -
NVIC_ICPR7
RW 0x00000000 Interrupt Clear-Pending Registers
0xE000E300 -
0xE000E31C
NVIC_IABR0 -
NVIC_IABR7
RO 0x00000000 Interrupt Active Bit Register
0xE000E400 -
0xE000E4EC
NVIC_IPR0 -
NVIC_IPR59
RW 0x00000000 Interrupt Priority Register
Reserved
31 43 0
INTLINESNUM