User guide

Nested Vectored Interrupt Controller

ID072410 Non-Confidential

6.2 NVIC functional description

The NVIC supports up to 240 interrupts each with up to 256 levels of priority. You can change

the priority of an interrupt dynamically. The NVIC and the processor core interface are closely

coupled, to enable low latency interrupt processing and efficient processing of late arriving

interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable

tail-chaining of interrupts.

You can only fully access the NVIC from privileged mode, but you can cause interrupts to enter

a pending state in user mode if you enable the Configuration and Control Register. Any other

user mode access causes a bus fault.

You can access all NVIC registers using byte, halfword, and word accesses unless otherwise

stated. NVIC registers are located within the SCS.

All NVIC registers and system debug registers are little-endian regardless of the endianness

state of the processor.

Processor exception handling is described in Exceptions on page 3-20.

6.2.1 Low power modes

Your implementation can include a Wake-up Interrupt Controller (WIC). This enables the

processor and NVIC to be put into a very low-power sleep mode leaving the WIC to identify

and prioritize interrupts.

The processor fully implements the Wait For Interrupt (

WFI

), Wait For Event (

WFE

) and the Send

Event (

SEV

) instructions. In addition, the processor also supports the use of SLEEPONEXIT, that

causes the processor core to enter sleep mode when it returns from an exception handler to

Thread mode. See the ARMv7-M Architecture Reference Manual for more information.

6.2.2 Level versus pulse interrupts

The processor supports both level and pulse interrupts. A level interrupt is held asserted until it

is cleared by the ISR accessing the device. A pulse interrupt is a variant of an edge model.You

must ensure that the pulse is sampled on the rising edge of the Cortex-M3 clock, FCLK, instead

of being asynchronous.

For level interrupts, if the signal is not deasserted before the return from the interrupt routine,

the interrupt again enters the pending state and re-activates. This is particularly useful for FIFO

and buffer-based devices because it ensures that they drain either by a single ISR or by repeated

invocations, with no extra work. This means that the device holds the signal in assert until the

device is empty.

A pulse interrupt can be reasserted during the ISR so that the interrupt can be in the pending

state and active at the same time. If another pulse arrives while the interrupt is still pending, the

interrupt will rmain pending and the ISR will run only once.

Pulse interrupts are mostly used for external signals and for rate or repeat signals.