User guide

System Control
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 4-4
ID072410 Non-Confidential
0xE000ED64 ID_ISAR1 RO 0x02111000 Instruction Set Attributes Register 1
0xE000ED68 ID_ISAR2 RO 0x21112231 Instruction Set Attributes Register 2
0xE000ED6C ID_ISAR3 RO 0x01111110 Instruction Set Attributes Register 3
0xE000ED70 ID_ISAR4 RO 0x01310132 Instruction Set Attributes Register 4
0xE000ED88 CPACR RW 0x00000000 Coprocessor Access Control Register
0xE000EF00 STIR WO 0x00000000 Software Triggered Interrupt Register
a. Bits [10:8] are reset to zero. The ENDIANNESS bit, bit [15], can reset to either state, depending on the implementation.
b. BFAR and MMFAR are the same physical register. Because of this, the BFARVALID and MMFARVALID bits are mutually
exclusive.
c. ID_DFR0 will read as 0 if no debug support is implemented.
Table 4-1 System control registers (continued)
Address Name Type Reset Description