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3.9 Exceptions

The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all

exceptions. When handling exceptions:

• All exceptions are handled in Handler mode.

• Processor state is automatically stored to the stack on an exception, and automatically

restored from the stack at the end of the Interrupt Service Routine (ISR).

• The vector is fetched in parallel to the state saving, enabling efficient interrupt entry.

The processor supports tail-chaining that enables back-to-back interrupts without the overhead

of state saving and restoration.

You configure the number of interrupts, and bits of interrupt priority, during implementation.

Software can choose only to enable a subset of the configured number of interrupts, and can

choose how many bits of the configured priorities to use.

Note

Vector table entries are compatible with interworking between ARM and Thumb instructions.

This causes bit [0] of the vector value to load into the Execution Program Status Register

(EPSR) T-bit on exception entry. All populated vectors in the vector table entries must have bit

[0] set. Creating a table entry with bit [0] clear generates an INVSTATE fault on the first

instruction of the handler corresponding to this vector.

3.9.1 Exception handling

The processor implements advanced exception and interrupt handling, as described in the

ARMv7-M Architecture Reference Manual.

To reduce interrupt latency, the processor implements both interrupt late-arrival and interrupt

tail-chaining mechanisms, as defined by the ARMv7-M architecture:

• There is a maximum of a twelve cycle latency from asserting the interrupt to execution of

the first instruction of the ISR when the memory being accessed has no wait states being

applied. The first instruction to be executed is fetched in parallel to the stack push.

• Returns from interrupts similarly take twelve cycles where the instruction being returned

to is fetched in parallel to the stack pop.

• Tail chaining requires six cycles when using zero wait state memory. No stack pushes or

pops are performed and only the instruction for the next ISR is fetched.

The processor exception model has the following implementation-defined behavior in addition

to the architecturally defined behavior:

• exceptions on stacking from HardFault to NMI lockup at NMI priority

• exceptions on unstacking from NMI to HardFault lockup at HardFault priority.

To minimize interrupt latency, the processor abandons any divide instruction to take any

pending interrupt. On return from the interrupt handler, the processor restarts the divide

instruction from the beginning The processor implements the Interruptible-continuable

Instruction field. Load multiple (

LDM

) operations and store multiple (

STM

) operations are

interruptible. The EPSR holds the information required to continue the load or store multiple

from the point where the interrupt occurred.