User guide

Programmers Model

ID072410 Non-Confidential

See the ARMv7-M Architecture Reference Manual for more information about the memory

model.

3.4.1 Private peripheral bus

The internal Private Peripheral Bus (PPB) interface provides access to:

• the Instrumentation Trace Macrocell (ITM)

• the Data Watchpoint and Trace (DWT)

• the Flashpatch and Breakpoint (FPB)

• the System Control Space (SCS), including the MPU and the NVIC.

The external PPB interface provides access to:

•the TPIU

• the ETM

• the ROM table

• implementation-specific areas of the PPB memory map.

3.4.2 Unaligned accesses that cross regions

The Cortex-M3 processor supports ARMv7 unaligned accesses, and performs all accesses as

single, unaligned accesses. They are converted into two or more aligned accesses by the DCode

and System bus interfaces.

Note

All Cortex-M3 external accesses are aligned.

Unaligned support is only available for load/store singles (

LDR

LDRH, STR, STRH

). Load/store

double already supports word aligned accesses, but does not permit other unaligned accesses,

and generates a fault if this is attempted.

Unaligned accesses that cross memory map boundaries are architecturally Unpredictable. The

processor behavior is boundary dependent, as follows:

• DCode accesses wrap within the region. For example, an unaligned halfword access to the

last byte of Code space (

0x1FFFFFFF

) is converted by the DCode interface into a byte

access to

0x1FFFFFFF

followed by a byte access to

0x00000000

Peripheral bit-band Alias region. Data accesses are aliases. Instruction accesses are not aliases.

External RAM Instruction fetches and data accesses are performed over the system bus.

External Device Instruction fetches and data accesses are performed over the system bus.

Private Peripheral Bus External and internal Private Peripheral Bus (PPB) interfaces. See Private peripheral bus.

This memory region is Execute Never (XN), and so instruction fetches are prohibited. An MPU, if present,

cannot change this.

System System segment for vendor system peripherals. This memory region is XN, and so instruction fetches are

prohibited. An MPU, if present, cannot change this.

Table 3-2 Memory regions (continued)

Memory Map Region