User guide

Programmers Model
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 3-7
ID072410 Non-Confidential
Push Push PUSH {<reglist>} 1 + N
Push with link register
PUSH {<reglist>, LR} 1 + N
Pop Pop
POP {<reglist>} 1 + N
Pop and return
POP {<reglist>, PC} 1 + N + P
Semaphore Load exclusive
LDREX Rd, [Rn, #<imm>] 2
Load exclusive half
LDREXH Rd, [Rn] 2
Load exclusive byte
LDREXB Rd, [Rn] 2
Store exclusive
STREX Rd, Rt, [Rn, #<imm>] 2
Store exclusive half
STREXH Rd, Rt, [Rn] 2
Store exclusive byte
STREXB Rd, Rt, [Rn] 2
Clear exclusive monitor
CLREX 1
Branch Conditional
B<cc> <label>
1 or 1 + P
d
Unconditional B <label> 1 + P
With link
BL <label> 1 + P
With exchange
BX Rm 1 + P
With link and exchange
BLX Rm 1 + P
Branch if zero
CBZ Rn, <label>
1 or 1 + P
d
Branch if non-zero CBNZ Rn, <label>
1 or 1 + P
d
Byte table branch TBB [Rn, Rm] 2 + P
Halfword table branch
TBH [Rn, Rm, LSL#1] 2 + P
State change Supervisor call
SVC #<imm> -
If-then-else
IT... <cond>
1
e
Disable interrupts CPSID <flags> 1 or 2
Enable interrupts
CPSIE <flags> 1 or 2
Read special register
MRS Rd, <specreg> 1 or 2
Write special register
MSR <specreg>, Rn 1 or 2
Breakpoint
BKPT #<imm> -
Extend Signed halfword to word
SXTH Rd, <op2> 1
Signed byte to word
SXTB Rd, <op2> 1
Unsigned halfword
UXTH Rd, <op2> 1
Unsigned byte
UXTB Rd, <op2> 1
Table 3-1 Cortex-M3 instruction set summary (continued)
Operation Description Assembler Cycles