User guide

Programmers Model
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 3-5
ID072410 Non-Confidential
Subtract Subtract SUB Rd, Rn, <op2> 1
Subtract with borrow
SBC Rd, Rn, <op2> 1
Reverse
RSB Rd, Rn, <op2> 1
Multiply Multiply
MUL Rd, Rn, Rm 1
Multiply accumulate
MLA Rd, Rn, Rm 2
Multiply subtract
MLS Rd, Rn, Rm 2
Long signed
SMULL RdLo, RdHi, Rn, Rm
3 to 5
a
Long unsigned UMULL RdLo, RdHi, Rn, Rm
3 to 5
a
Long signed accumulate SMLAL RdLo, RdHi, Rn, Rm
4 to 7
a
Long unsigned accumulate UMLAL RdLo, RdHi, Rn, Rm
4 to 7
a
Divide Signed SDIV Rd, Rn, Rm
2 to 12
b
Unsigned UDIV Rd, Rn, Rm
2 to 12
b
Saturate Signed SSAT Rd, #<imm>, <op2> 1
Unsigned
USAT Rd, #<imm>, <op2> 1
Compare Compare
CMP Rn, <op2> 1
Negative
CMN Rn, <op2> 1
Logical AND
AND Rd, Rn, <op2> 1
Exclusive OR
EOR Rd, Rn, <op2> 1
OR
ORR Rd, Rn, <op2> 1
OR NOT
ORN Rd, Rn, <op2> 1
Bit clear
BIC Rd, Rn, <op2> 1
Move NOT
MVN Rd, <op2> 1
AND test
TST Rn, <op2> 1
Exclusive OR test
TEQ Rn, <op1>
Shift Logical shift left LSL Rd, Rn, #<imm> 1
Logical shift left
LSL Rd, Rn, Rs 1
Logical shift right
LSR Rd, Rn, #<imm> 1
Logical shift right
LSR Rd, Rn, Rs 1
Arithmetic shift right
ASR Rd, Rn, #<imm> 1
Arithmetic shift right
ASR Rd, Rn, Rs 1
Table 3-1 Cortex-M3 instruction set summary (continued)
Operation Description Assembler Cycles