User guide

Introduction

ID072410 Non-Confidential

• Errata fixes to the r1p0 release.

1.6.3 Differences in functionality between r1p1 and r2p0

In summary, the differences in functionality include:

• Implementation time options have been added to select between different levels of debug

and trace support. This has replaced the previous TIEOFF_FPBEN and

TIEOFF_TRCENA options.

• New implementation option to enable the resetting of all registers within the processor.

• Architectural clock gating inclusion is now controlled using one implementation option.

• DBGRESTART input and DBGRESTARTED output have been added for use in

debugging multi-core systems. See the ARMv7-M Architecture Reference Manual for

more information.

• SLEEPHOLDREQn input and SLEEPHOLDACKn have been added to enable the

extension of SLEEPING.

• The APB interface has been upgraded from v2.0 to v3.0.

• A new output signal called INTERNALSTATE has been added that enables observation

of some of the internal state of the core if the OBSERVATION implementation option is

used.

• Added support for fault-robust implementations.

• An Auxiliary Control Register has been added with new functionality disable bits to:

— stop interruption of load/store multiples, divides and multiplies

— stop IT folding

— disable the write buffers in Cortex-M3 for default memory map accesses.

• The STKALIGN bit reset value in the Configuration and Control Register at address

0xE000ED14

has been inverted. The reset value is now 1, which means that the stack frame

is 8-byte aligned by default.

• Addition of a Wake-up Interrupt Controller to minimize logic in the always clocked

domain during sleep.

• Addition of FIXHMASTERTYPE pin to prevent debugger marking AHB transactions

as core data side if required.

• Improved sequential information for data accesses. Before r2p0 HPROT for sequential

data accesses would change from SEQ to NSEQ if wait-states were inserted for the

previous access. r2p0 maintains the SEQ information.

• Errata fixes to the r1p1 release.

1.6.4 Differences in functionality between r2p0 and r2p1

In summary, the differences in functionality include:

• New implementation option to ensure constant AHB control during wait-stated transfers.

• New implementation option to remove the bit-banding logic.

• MPUDISABLE input added to disable the MPU via hardware.