User guide

Introduction

ID072410 Non-Confidential

1.6 Product revisions

This section summarizes the differences in functionality between the different releases of this

processor:

• Differences in functionality between r0p0 and r1p0

• Differences in functionality between r1p0 and r1p1

• Differences in functionality between r1p1 and r2p0 on page 1-10

• Differences in functionality between r2p0 and r2p1 on page 1-10.

1.6.1 Differences in functionality between r0p0 and r1p0

In summary, the differences in functionality include:

• Addition of configurable data value comparison to the DWT module.

• Addition of a MATCHED bit to DWT_FUNCTION.

• Addition of configurable ETMFIFOFULL stalling functionality to the processor and the

ETM.

• Addition of SWV Mode to the ITM.

• CPUID Base Register VARIANT field changed to indicate Rev1.

• Cortex-M3 Rev0 Bit-band accesses in BE8 mode required access sizes to be byte.

Cortex-M3 Rev1 has been changed so that BE8 bit-band accesses function with any

access size.

• Addition of a configuration bit called STKALIGN to ensure that all exceptions have

eight-byte stack alignment.

• Addition of the Auxiliary Fault Status Register at address

0xE000ED3C

. To set this register,

a 32-bit input bus called AUXFAULT has been added.

• Addition of HTM support.

• ICode and DCode cacheable and bufferable HPROT values permanently tied to

write-through.

• Addition of the SWJ-DP. This is the standard CoreSight

™

debug port that combines

JTAG-DP and SW-DP.

• Addition of DWT_PCSR Register at address

0xE000101C

• Errata fixes to the r0p0 release.

1.6.2 Differences in functionality between r1p0 and r1p1

In summary, the differences in functionality include:

• Data value matching for watchpoint generation has been made implementation time

configurable.

• Architectural clock gating in the ETM is configurable at implementation.

• DAPCLKEN was required to be a static signal in r0p0 and r1p0. This requirement has

been removed for r1p1.

• SLEEPING signal now suppressed until current outstanding instruction fetch has

completed.