User guide

Introduction
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 1-3
ID072410 Non-Confidential
1.2 Features
The Cortex-M3 processor incorporates:
• a processor core
•a Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core
to achieve low latency interrupt processing
• multiple high-performance bus interfaces
• a low-cost debug solution with the optional ability to:
— implement breakpoints and code patches
— implement watchpoints, tracing, and system profiling
— support
printf() style debugging.
— bridge to a Trace Port Analyzer (TPA).
• an optional Memory Protection Unit (MPU).