User guide

Glossary
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Memory coherency A memory is coherent if the value read by a data read or instruction fetch is the value that was
most recently written to that location. Memory coherency is made difficult when there are
multiple possible physical locations that are involved, such as a system that has main memory,
a write buffer and a cache.
Memory Protection Unit (MPU)
Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does
not modify addresses.
Microprocessor See Processor.
Monitor debug-mode
One of two mutually exclusive debug modes. In Monitor debug-mode the processor enables a
software abort handler provided by the debug monitor or operating system debug task. When a
breakpoint or watchpoint is encountered, this enables vital system interrupts to continue to be
serviced while normal program execution is suspended.
See also Halt mode.
MPU See Memory Protection Unit.
Multi-layer An interconnect scheme similar to a cross-bar switch. Each master on the interconnect has a
direct link to each slave, The link is not shared with other masters. This enables each master to
process transfers in parallel with other masters. Contention only occurs in a multi-layer
interconnect at a payload destination, typically the slave.
Nested Vectored Interrupt Controller (NVIC)
Provides the processor with configurable interrupt handling abilities.
NMI See Non-maskable interrupt
Non-maskable interrupt
A NonMaskable Interrupt (NMI) can be signalled by a peripheral or triggered by software. This
is the highest priority exception other than reset. It is permanently enabled and has a fixed
priority of -2. NMIs cannot be:
• masked or prevented from activation by any other exception
• preempted by any exception other than Reset.
NVIC See Nested Vectored Interrupt Controller.
Penalty The number of cycles in which no useful Execute stage pipeline activity can occur because an
instruction flow is different from that assumed or predicted.
PFU See Prefetch Unit.
PMU See Power Management Unit.
Power Management Unit (PMU)
Provides the processor with power management capability.
Power-on reset See Cold reset.
PPB See Private Peripheral Bus.
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline
before the preceding instructions have finished executing. Prefetching an instruction does not
mean that the instruction has to be executed.