User guide

Glossary
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. Glossary-2
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Advanced Peripheral Bus (APB)
A simpler bus protocol than AXI and AHB. It is designed for use with ancillary or
general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports.
Connection to the main system bus is through a system-to-peripheral bus bridge that helps to
reduce system power consumption.
AHB See Advanced High-performance Bus.
AHB Access Port (AHB-AP)
An optional component of the DAP that provides an AHB interface to a SoC.
AHB-AP See AHB Access Port.
AHB-Lite A subset of the full AMBA AHB protocol specification. It provides all of the basic functions
required by the majority of AMBA AHB slave and master designs, particularly when used with
a multi-layer AMBA interconnect. In most cases, the extra facilities provided by a full AMBA
AHB interface are implemented more efficiently by using an AMBA AXI protocol interface.
AHB Trace Macrocell
A hardware macrocell that, when connected to a processor core, outputs data trace information
on a trace port.
Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size
is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and
two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses
that are divisible by four and two respectively.
AMBA See Advanced Microcontroller Bus Architecture.
Advanced Trace Bus (ATB)
A bus used by trace devices to share CoreSight capture resources.
APB See Advanced Peripheral Bus.
Application Specific Integrated Circuit (ASIC)
An integrated circuit that has been designed to perform a specific application function. It can be
custom-built or mass-produced.
Architecture The organization of hardware and/or software that characterizes a processor and its attached
components, and enables devices with similar characteristics to be grouped together when
describing their behavior, for example, Harvard architecture, instruction set architecture,
ARMv7-M architecture.
ARM instruction An instruction of the ARM Instruction Set Architecture (ISA). These cannot be executed by the
Cortex-M3 processor.
ARM state The processor state in which the processor executes the instructions of the ARM ISA. The
processor only operates in Thumb state, never in ARM state.
ASIC See Application Specific Integrated Circuit.
ATB See Advanced Trace Bus.
ATB bridge A synchronous ATB bridge provides a register slice to facilitate timing closure through the
addition of a pipeline stage. It also provides a unidirectional link between two synchronous ATB
domains.
An asynchronous ATB bridge provides a unidirectional link between two ATB domains with
asynchronous clocks. It is intended to support connection of components with ATB ports
residing in different clock domains.