User guide

Trace Port Interface Unit
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 11-6
ID072410 Non-Confidential
The following sections describe the TPIU registers whose implementation is specific to this
processor. The Formatter, Integration Mode Control, and Claim Tag registers are described in
the CoreSight Components Technical Reference Manual. Other registers are described in the
ARMv7-M Architecture Reference Manual.
11.3.1 Asynchronous Clock Prescaler Register, TPIU_ACPR
The TPIU_ACPR characteristics are:
Purpose Scales the baud rate of the asynchronous output.
Usage constraints There are no usage constraints.
Configurations This register is available in all processor configurations.
Attributes See Table 11-1 on page 11-5.
Figure 11-2 shows the TPIU_ACPR bit assignments.
Figure 11-2 TPIU_ACPR bit assignments
Table 11-2 shows the TPIU_ACPR bit assignments.
11.3.2 Formatter and Flush Status Register, TPIU_FFSR
The TPIU_FFSR characteristics are:
Purpose Indicates the status of the TPIU formatter.
Usage constraints There are no usage constraints.
Configurations This register is available in all processor configurations.
Attributes See Table 11-1 on page 11-5.
Figure 11-3 shows the TPIU_FFSR bit assignments.
Figure 11-3 TPIU_FFSR bit assignments
31 13 0
Reserved
12
PRESCALER
Table 11-2 TPIU_ACPR bit assignments
Bits Name Function
[31:13] - Reserved. RAZ/SBZP.
[12:0] PRESCALER Divisor for TRACECLKIN is Prescaler + 1.
31 2 0
Reserved
1
FlInProg
3
FtStopped
TCPresent
FtNonStop
4