User guide

Trace Port Interface Unit

ID072410 Non-Confidential

11.1 About the Cortex-M3 TPIU

The Cortex-M3 TPIU is an optional component that acts as a bridge between the on-chip trace

data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell

(ITM), with separate IDs, to a data stream. The TPIU encapsulates IDs where required, and the

data stream is then captured by a Trace Port Analyzer (TPA).

The Cortex-M3 TPIU is specially designed for low-cost debug. It is a special version of the

CoreSight TPIU. Your implementation can replace the Cortex-M3 TPIU with other CoreSight

components if your implementation requires the additional features of the CoreSight TPIU.

In this chapter, the term TPIU refers to the Cortex-M3 TPIU. For information about the

CoreSight TPIU, see the ARM CoreSight Components Technical Reference Manual.